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[ AK8857VQ] ms1189-e-01 2010/12 -1- overview the AK8857VQ is a single-chip digital video decoder for composite and s-video video signals. in case of composite video signal, it can decode two inputs at the same time. its output data is in ycbcr format, compliant with itu-r bt.601. its output in terface is itu-r bt.656 compliant. a simple ip conversion function is built inter nally and the output pixel size al so can easily be changed using this function. the operating temperature range is ? 40c to 85c. the package is 64-terminal lqfp. features decodes two inputs of composite vi deo signals ntsc (j, m, 4.43), pal (b , d, g, h, i, m, n, nc, 60), secam at the same time. decodes s-video video signals ntsc (j, m, 4.43), pal (b, d, g, h, i, m, n, nc, 60), secam. four input channels, with internal video switch. 11-bit 54mhz adc 1 channel. digital pga. adaptive automatic gain control (agc). auto color control (acc) simple ip conversion func tion (line repeating process). image adjustment (contrast, satura tion, brightness, hue, sharpness). automatic input signal detection. adaptive 2-d y/c separation. itu-r bt.656 and itu-r bt.601 format output (with 4:2:2_8 bit parallel_eav/sav). supported output pixel size : 720x487, 720x576, wvga, vga, wqvga, qvga sync signal timing for external output : hsync/hact, vsync/vact, field, dvalid closed-caption signal decodi ng (output via register). vbid(cgms-a) signal decoding (crcc decode) (output via register). wss signal decoding ( output via register). power down function. i 2 c control. 1.70~2.00 v core power supply. 1.70~3.60 v interface power supply. operating temperature range: ? 40c to 85c. 64-pin lqfp package. *because the data is sampling to a fi xed clock, it may not fullfilled the itu-r bt.656 standard interface. AK8857VQ dual channel digital video decoder
[AK8857VQ] ms1189-e-01 2010/12 -2- 1.functional block diagram in this specification, the output pins above the dtclk pin on the right side of this block di agram is called [a block] and the output pins below the dtclk pin is called [b block]. test logic microprocessor interface aaf vref avss avdd dvdd dvss pvdd1 pvdd2 vcom vrn iref vrp ain1 test0 test1 clamp decimation filter scaling & i/p buffer clock module pll 11-bit adc sela rstn pdn sda scl xti xto hd _ act _ a vd_act_a data_a[7:0] oe_a sync separation composite decode x 2 or y/c docode x 1 mux aaf clamp ain2 digital pga1 decimation filter sync separation digital pga2 mux dtclk nsig _ b nsig _ a ain3 ain4 mux dvalid_b field _ b vd_act_b dvalid_a hd_act_b field_a data _ b [ 7:0 ] oe_b
[ AK8857VQ] ms1189-e-01 2010/12 -3- 2.pin assignment ? 64 pins lqfp 1 2 3 4 5 6 7 8 9 10111213141516 39 383736353433 46 45 4443424140 48 47 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 sela sda scl avdd xto avss xti vrn vrp vcom iref pdn oe_b pvdd2 oe_a rstn field_a dtclk pvdd1 dvalid_a hd_act_a vd_act_a data_a7 data_a6 dvss dvdd pvdd1 field_b data_b7 hd_act_b vd_act_b dvalid_b test0 nsig_b test1 dvdd dvss ppdd1 data_b0 data_b1 data_b2 data_b3 data_b4 data_b5 data_b6 pvdd1 dvss nsig_ a a vss a vdd a in2 a in3 a vdd a in4 a vss dvss pvdd1 data_a0 data_a1 data_a2 data_a3 data_a4 a in1 data_a5
[ AK8857VQ] ms1189-e-01 2010/12 -4- 3.pin functions pin no. symbol p/s 1 i/o 2 functional description 1 ain1 a i analog video signal input pin. c onnect via 0.033 f capacitor and voltage-splitting resistors as shown in page 121. if it is not used, connect to nc. 2 avdd a p analog ground pin. 3 ain2 a i analog video signal input pin. c onnect via 0.033 f capacitor and voltage-splitting resistors as shown in page 121. if it is not used, connect to nc. 4 avss a g analog ground pin. 5 ain3 a i analog video signal input pin. c onnect via 0.033 f capacitor and voltage-splitting resistors as shown in page 121. if it is not used, connect to nc. 6 avdd a p analog ground pin. 7 ain4 a i analog video signal input pin. c onnect via 0.033 f capacitor and voltage-splitting resistors as shown in page 121. if it is not used, connect to nc. 8 avss a g analog ground pin. 9 dvss d g digital ground pin. 10 pvdd1 p1 p i/o power supply pin. 11 data_a0 p1 o ( i ) a block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status. 12 data_a1 p1 o ( i ) a block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status. 13 data_a2 p1 o ( i ) a block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status. 14 data_a3 p1 o ( i ) a block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status. 15 data_a4 p1 o ( i ) a block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status. 16 data_a5 p1 o ( i ) a block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status. 17 dvdd d p digital power supply pin. 18 dvss d g digital ground pin. 19 pvdd1 p1 p i/o power supply pin. 20 data_a6 p1 o ( i ) a block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status.
[ AK8857VQ] ms1189-e-01 2010/12 -5- pin no. symbol p/s 1 i/o 2 functional description 21 data_a7 p1 o ( i ) a block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status. 22 vd_act_a p1 o ( i ) a block vd(vertical drive) / vact (vertical active) signal output pin. vd signal output / vact signal out put can be selected by register setting. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status. 23 hd_act_a p1 o ( i ) a block hd(horizontal drive) / hact(horizontal active) signal output pin. hd signal output / ha ct signal output can be selected by register setting. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status. 24 dvalid_a p1 o ( i ) a block dvalid signal output pin. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status. 25 field_a p1 o ( i ) a block field signal output pin. used as i/o pin in test mode. see table below for relation of output to oe_a, pdn and rstn pin status. 26 pvdd1 p1 p i/o power supply pin. 27 dtclk p1 o data clock output pin. approx. 27 mhz clock output. see table below for relation of output to oe_a, oe_b, pdn and rstn pin status. 28 field_b p1 o ( i ) b block field signal output pin. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status. 29 dvalid_b p1 o ( i ) b block dvalid signal output pin. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status. 30 hd_act_b p1 o ( i ) b block hd(horizontal drive) / hact(horizontal active) signal output pin. hd signal output / hact signal out put can be selected by register setting. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status. 31 vd_act_b p1 o ( i ) b block vd(vertical drive) / vact(vertical active) signal output pin. vd signal output / vact signal out put can be selected by register setting. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status.
[ AK8857VQ] ms1189-e-01 2010/12 -6- pin no. symbol p/s 1 i/o 2 functional description 32 data_b7 p1 o ( i ) b block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status. 33 dvss d g digital ground pin. 34 pvdd1 p1 p i/o power supply pin. 35 data_b6 p1 o ( i ) b block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status. 36 data_b5 p1 o ( i ) b block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status. 37 data_b4 p1 o ( i ) b block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status. 38 data_b3 p1 o ( i ) b block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status. 39 data_b2 p1 o ( i ) b block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status. 40 data_b1 p1 o ( i ) b block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status. 41 data_b0 p1 o ( i ) b block data output pin. used as i/o pin in test mode. see table below for relation of output to oe_b, pdn and rstn pin status. 42 pvdd1 p1 p i/o power supply pin. 43 dvss d g digital ground pin. 44 dvdd d p digital power supply pin. 45 test0 p2 i pin for test mode setting. connect to dvss. 46 test1 p2 i pin for test mode setting. connect to dvss. 47 nsig_b p2 o ( i ) shows status of synchronization with input signal of b block. low: signal present (synchronized). high: signal not present or not synchronized. see table below for relation of output to oe_b, pdn, rstn pin status. 48 nsig_a p2 o ( i ) shows status of synchronization with input signal of a block. low: signal present (synchronized). high: signal not present or not synchronized. see table below for relation of output to oe_a, pdn, rstn pin status.
[ AK8857VQ] ms1189-e-01 2010/12 -7- pin no. symbol p/s 1 i/o 2 functional description 49 oe_b p2 i b block output enable pin. l: digital output pin in hi-z output mode. h: data output mode. hi-z input to oe_b pin is prohibited. 50 oe_a p2 i a block output enable pin. l: digital output pin in hi-z output mode. h: data output mode. hi-z input to oe_a pin is prohibited. 51 pvdd2 p2 p microprocessor i/f power supply pin. 52 rstn p2 i reset signal input pin. hi-z input is prohibited. l: reset. h: normal operation. 53 pdn p2 i power-down control pin. hi-z input is prohibited. l: power-down. h: normal operation. 54 sda p2 i/o i 2 c data pin. connect to pvdd2 via a pull-up register. hi-z input possible when rstn=l. will not accept sda input during reset sequence. 55 scl p2 i i 2 c clock input pin. use pvdd2 or lower for input. hi-z input possible when pdn=l. will not accept scl input during reset sequence. 56 sela p2 i ( o ) i 2 c bus address selector pin. pvdd2 connection: slave address [0x8a] dvss connection: slave address [0x88] 57 avdd a p analog power supply pin. 58 xto a o crystal connection pin. connect to digital ground via 22 pf capacitor as shown in sec. 10. use 24.576 mhz crystal. when pdn=l, output level is dvss. if crystal is not used, connect to nc or dvss. 59 avss a g analog ground pin. 60 xti a i crystal connection pin. connect to digital ground via 22 pf capacitor as shown in sec. 10. use 24.576 mhz crystal resonator. for input from 24.576 mhz crystal oscillator, use this pin. 61 vrn a o internal reference negative voltage pin for ad converter. connect to avss via 0.1 f ceramic capacitor. 62 iref a o reference current setting pin. connect to ground via 6.8 k ? ( 1% accuracy) resistor.
[ AK8857VQ] ms1189-e-01 2010/12 -8- pin no. symbol p/s 1 i/o 2 functional description 63 vrp a o internal reference positive voltage pin for ad converter. connect to avss via 0.1 f ceramic capacitor. 64 vcom a o common internal voltage for ad convertor. connect to avss via 0.1 f ceramic capacitor. 1 power supply a: avdd, d: dvdd, p1: pvdd1, p2: pvdd2 2 input/output o: output pin, i: in tput pin, i/o:input/output pin, p: power supply pin,g:ground connect- ion pin. output pin status as determined by oe _a, oe_b, pdn, and rstn pin status. oe_a, oe_b (*2) pdn rstn output1 (*2) output2 (*2) l x x hi-z output l output h l x l output l output l l output l output h h h default data out (*3) default data out (*3) 2 output1: (a block) data_a[7:0], hd_act_ a, vd_act_a, dvalid_a, field_a (b block) data_b[7:0], hd_act_ b, vd_act_b, dvalid_b, field_b dtclk. if oe_a and oe_b both are in low conditi on, the dtclk pin output is hi-z. output2: nsig_a, nsig_b if (oe_a=h or oe_b=h) and pdn=h just after pow er is turned on, output pin status will be indefinite until internal state is determined by reset sequence. 3 in the absence of ain signal input, output will be black data ((y=0x10, cb/cr=0x80). (blueback output can be obtained by register setting.)
[ AK8857VQ] ms1189-e-01 2010/12 -9- 4. electrical specifications (1) absolute maximum ratings parameter min max units notes supply voltage avdd, dvdd, pvdd1, pcdd2 ? 0.3 ? 0.3 2.2 4.2 v v analog input pin voltage a (vina) ? 0.3 avdd + 0.3 ( 2.2) v digital output pin voltage p1 (viop1) ? 0.3 pvdd1 + 0.3 ( 4.2) v (*1) digital output pin voltage p2 (viop2) ? 0.3 pvdd2 + 0.3 ( 4.2) v (*2) input pin current (iin) (except for power supply pin) ? 10 10 ma storage temperature ? 40 125 oc *the above supply voltages are referenced to ground pins (dvss= avss) at 0 v (the reference voltage). all power supply grounds (avss, dvss) shoul d be at the same electric potential. if digital output pins are connected to data bus, the data bus operating voltage should be in the same range as shown above for the digital output pin. (*1) data_a[7:0], hd_act_a, vd _act_a, dvalid_a, field_a, data_b[7:0], hd_act_b, vd_a ct_b, dvalid_b, field_b, dtclk. (*2) oe_a, oe_b, sela, pdn, rstn, sda, scl, nsig_a, nsig_b, test0, test1. (2) recommended operating conditions parameter min typ max units condition analog supply voltage (avdd) digital supply voltage (dvdd) 1.70 1.80 2.00 v avdd=dvdd i/o supply voltage (pvdd1) mpu i/f supply voltage (pvdd2) 1.70 1.80 3.60 v pvdd1 dvdd pvdd2 dvdd operating temp. (ta) ? 40 85 oc the above supply voltages are referenced to ground pins (dvss= avss) at 0 v (the reference voltage). all power supply grounds (avss, dvss) shoul d be at the same electric potential.
[ AK8857VQ] ms1189-e-01 2010/12 -10- (3) dc characteristics where no specific condition is indicated in the following table, the supply voltage range is the same as that shown for the reco mmended operating conditions in 4-2 above. parameter symbol min typ max units condition 0.8pvdd2 v case *1 digital p2 input high voltage vpih 0.7pvdd2 v case *2 0.2pvdd2 v case *1 digital p2 input low voltage vpil 0.3pvdd2 v case *2 digital input leak current il 10 ua digital p1 output high voltage vp1oh 0.8pvdd1 v ioh = -600ua digital p1 output low voltage vp1ol 0.2pvdd1 v iol = 1ma digital p2 output high voltage vp2oh 0.8pvdd2 v ioh = -600ua digital p2 output low voltage vp2ol 0.2pvdd2 v iol = 1ma i 2 c (sda)l output volc 0.4 0.2 pvdd2 v iolc = 3ma pvdd2 2.0v pvdd2<2.0v *1: < dvdd = 1.70v~2.00v, dvdd pvdd1<2.70v, dvdd pvdd2<2.70v, ta: -40~85 ? c > *2: < dvdd = 1.70v~2.00v, 2.70v pvdd1 3.60v, 2.70v pvdd2 3.60v, ta: -40~85 ? c > definition of above input/output terms digital p2 input : collective term for sda, sc l, sela, oe_a, oe_b, pdn, rstn, test0, test1 pin inputs. digital p1 output : collective term for data_a[7 :0], hd_act_a, vd_act_a, dvalid_a, field_a, data_b[7:0], hd_act_b, vd_act_b, dv alid_b, field_b, dtclk pin outputs. digital p2 output : collective term for nsig_a, nsig_b pin outputs. sda pin output: not termed digital pin out put unless otherwise specifically stated.
[ AK8857VQ] ms1189-e-01 2010/12 -11- (4) analog characteristics (avdd=1.8v, temp.25 ? c) selector clamp parameter symbol min typ max units condition maximum input range vimx 0 0.50 0.60 v pp adc output data is fullcode when input range is 0.6vpp input. ad converter parameter symbol min typ max units condition resolution res 11 bit operating clock frequency fs 27 mhz adc:54mhz integral nonlinearity inl 2.0 +4.0 -4.0 lsb fs=27mhz, input range = 0.5vpp differential nonlinearity dnl 0.5 +1.5 -1.0 lsb fs=27mhz, input range = 0.5vpp s/n sn 54 db s/(n+d) snd 52 db fin=1mhz*, fs=27mhz, input range = 0.5vpp adc internal common voltage vcom 0.96 v adc internal positive vref vrp 1.28 v adc internal negative vref vrn 0.64 v *fin = ain input signal frequency aaf (anti-aliasing filter) parameter symbol min typ max units condition pass band ripple gp -1 +1 db 6mhz stop band blocking gs 20 35 db 27mhz (5) current consumption (at dvdd = avdd = pvdd1 = pvdd2 = 1.8v, ta = ? 40 ~ 85 ? c) (*1) parameter symbol min typ max units condition (active mode) total idd1 86 130 ma cvbs : 2ch idd2 63 ma cvbs : 1ch (*2) idd3 75 112 ma s-video (*2) analog block aidd 39 ma cvbs : 2ch with xtal crystal connected. digital block didd 34 ma i/o block pidd 13 ma cvbs : 2ch load condition: cl=12pf, 24pf* (*dtclk pin) (power down mode) total sidd 1 20 ua analog block asidd 1 ua digital block dsidd 1 ua i/o block psidd 1 ua pdn=l(dvss) (*3) (*1) with ntsc-j 100% color bar input. (*2) reference value. during a block is se t to output, b block is set to [no decode].
[ AK8857VQ] ms1189-e-01 2010/12 -12- (*3)to perform power-down, oe_a, oe_b and rstn pins must always be brought to the voltage polarity to be used or to ground level. (6) crystal circuit block (ta : -40~85 ? c) parameter symbol min typ max units condition frequency f 0 27 mhz frequency tolerance f / f 100 ppm load capacitance cl 15 pf effective equivalent resistance re 100 ? (*1) crystal parallel capacitance co 0.9 pf xti terminal external connection load capacitance cxi 22 pf cl=15pf xto terminal external connection load capacitance cxo 22 pf cl=15pf (*1) effective equivalent resistance generally may be taken as re = r1 x (1+co/cl) 2 , where r1 is the crystal series equivalent resistance. example connection xti pin xto pin rf rd ( * 2 ) cxi = 22pf cxo = 22pf a k8857vq internal circuit external circuit (*2) determine need for and appropriate value of limiting resistance (rd) in accordance with the crystal s pecifications. AK8857VQ is hereafter the ?ak8857?.
[ AK8857VQ] ms1189-e-01 2010/12 -13- 5. ac timing (dvdd=1.70v~2.00v, pvdd1=dvdd~3.60v, pvdd2=dvdd~3.60v, -40~85 ? c) load condition: cl=12pf, 24pf(dtclk pin) (1) clock input set ak8857 clock input as follows. fclk tclkl tclkh vih 1/2 level vil parameter symbol min typ max units input clk fclk 27 mhz clk pulse width h tclkh 15 nsec clk pulse width l tclkl 15 nsec frequency tolerance 100 ppm (2) clock output (dtclk output) parameter symbol min typ max units output data format 54 601,vga, wvga progressive output. dtclk fdtclk 27 mhz 601,vga, wvga other than progressive output. fdtclk 0.5pvdd1
[ AK8857VQ] ms1189-e-01 2010/12 -14- (3) output data timing data_a[7:0], hd_act_a, vd_act_a, field_ a, dvalid_a, data_a[7:0], hd_act_a, vd_act_a, field_a, dvalid_a tds 0.5pvdd1 tdh dtclk output data 0.5pvdd1 parameter symbol min typ max units dtclk 10 nsec 27mhz output data setup time tds 5 nsec 54mhz 10 nsec 27mhz output data hold time tdh 5 nsec 54mhz (4) register reset timing resettiming rstn fclk vil parameter symbol min typ max units notes rstn pulse width resettiming 100 (3.7) clk (usec) based on clock leading edge note. clock input is necessa ry for reset operation. rstn pin must be pulled low following clock application.
[ AK8857VQ] ms1189-e-01 2010/12 -15- (5) power-down sequence and reset sequence after power-down reset must be applied for at least 2048 clock cycl es (or 83.33 s) before setting pdn (pdn=low). reset must be applied for at least 5 ms after pdn release (pdn=hi). vih vil vih clkin rstn pdn ress resh gnd parameter symbol min typ max units reset width before setting pdn ress 2048 (75.85) clk (usec) reset width after pdn release resh 5 msec to perform power-down, all control signals must alwa ys be brought to the voltage polarity to be used or to ground level. for any power supply removal, all power supplies must be removed. clock input is necessary for resetting. the power-down sequence for connection of the crystal is as follows. a vdd/dvdd pvdd1/pvdd2 pdn rstn 5 ms (max) to stable crystal oscillator xti vcom,vrp,vr resh ? 5ms(min) pdn release * reference value
[ AK8857VQ] ms1189-e-01 2010/12 -16- (6) power-on reset at power-on, reset must be applied until the anal og reference voltage and current have stabilized. 1 (*1) the order of each power supply to be start up is not required. all the power supply must be on within 100msec during pdn pin status is low. vil respon vref rstn vdd pdn pwuptime parameter symbol min typ max units powerup time pwuptime 100 msec rstn pulse width respon 5 msec 1 clock input is necessary for resetting.
[ AK8857VQ] ms1189-e-01 2010/12 -17- (7) i 2 c bus input timing (dvdd=1.70v~2.00v, pvdd1=dvdd~3.60v, pvdd2=dvdd~3.60v, -40~85 ? c) (7-1) timing 1 tbuf thd : sta tr tf tsu : sto vih vil sda tf tr tsu : sta tlow vih vil scl parameter symbol min max units bus free time tbuf 1.3 usec hold time (start condition) thd:sta 0.6 usec clock pulse low time tlow 1.3 usec input signal rise time tr 300 nsec input signal fall time tf 300 nsec setup time(start condition) tsu:sta 0.6 usec setup time(stop condition) tsu:sto 0.6 usec note. the timing relating to the i 2 c bus is as stipulated by the i 2 c bus specification, and not determined by the device itself. for details, see i 2 c bus specification. (7-2) timing 2 vih vil sda vih vil scl thigh thd : dat tsu : dat parameter symbol min max units data setup time tsu:dat 100 1 nsec data hold time thd:dat 0.0 0.9 2 usec clock pulse high time thigh 0.6 usec 1 if i 2 c is used in standard mode, tsu: dat 250 ns is required. 2 this condition must be met if t he ak8854 is used with a bus that does not extend tlow (to use tlow at minimum specification).
[ AK8857VQ] ms1189-e-01 2010/12 -18- 6. functional description analog interface the ak8857 accepts composite video signal (cvbs), s-video input with 4 input pins available for this purpose. the decode signal is selected via the register (ainsel[4:0]). the ak8857 can decode 2ch of anolog video signal at the same time during composite video signal input. the digital output data is output to a block and b block output block. it is possible to switch the digital output data between a block and b block output bl ock. it also possible to select one of digital output data to be output at a block and b block output at the same time. definition analog input select a block and b block output video signal selection : [ainsel4: ainsel0] [00000]: [a]: ain1 (cvbs ), [b]: ain4(cvbs) [00001]: [a]: ain1 (cvbs ), [b]: ain3(cvbs) [00010]: [a]: ain1 (cvbs ), [b]: ain2(cvbs) [00011]: [a]: ain1 (c vbs), [b]: ain1(cvbs) [00100]: [a]: ain1 (cvbs), [b]: non-decode [00101]: [a]: ain2 (cvbs ), [b]: ain4(cvbs) [00110]: [a]: ain2 (cvbs), [b]: ain3(cvbs) [00111]: [a]: ain2 (cvbs), [b]: ain2(cvbs) [01000]: [a]: ain2 (cvbs ), [b]: ain1(cvbs) [01001]: [a]: ain2 (cvbs), [b]: non-decode [01010]: [a]: ain3 (cvbs ), [b]: ain4(cvbs) [01011]: [a]: ain3 (c vbs), [b]: ain3(cvbs) [01100]: [a]: ain3 (cvbs), [b]: ain2(cvbs) [01101]: [a]: ain3 (cvbs), [b]: ain1(cvbs) [01110]: [a]: ain3 (c vbs), [b]: non-decode [01111]: [a]: ain4 (cvbs), [b]: ain4(c vbs) [10000]: [a]: ain4(cvbs) , [b]: ain3(cvbs) [10001]: [a]: ain4 (cvbs ), [b]: ain2(cvbs) [10010]: [a]: ain4 (cvbs ), [b]: ain1(cvbs) [10011]: [a]: ain4 (cvbs), [b]: non-decode [10100]: [a]: non-decode, [b]: ain4 (cvbs) [10101]: [a]: non-decode, [b]: ain3(cvbs) [10110]: [a]: non-dec ode, [b]: ain2(cvbs) [10111]: [a]: non-dec ode, [b]: ain1(cvbs) [11000]: [a]: ain1(y) / ain3(c), [b]: non-decode [11001]: [a]: ain1(y) / ain3(c), [b]: ain1(y) / ain3(c) [11010]: [a]: ain2(y) / ain4(c), [b]: non-decode [11011]: [a]: ain2(y) / ain4(c), [b]: ain2(y) / ain4(c) [11100]: [a]: non-decode, [b]: ain1(y) / ain3(c) [11101]: [a]: non-decode, [b]: ain2(y) / ain4(c) the output block change to power-save mode when [n on-decode] is selected and digital circuit operational is stoped. this will low down the internal power consumption. the data output is low during this state. available pin : data_a[7:0], hd_act_a, vd _act_a, dvalid_a, field_a, data_b[7:0], hd_act_b, vd_act_b, dvalid_b, field_b, nsig_a, nsig_b pins. note: output control via pins oe_a, oe_b, pdn, and rstn takes priority, regardless of the above settings.
[ AK8857VQ] ms1189-e-01 2010/12 -19- analog band limiting filter and analog clamp circuit ? analog band limiting filter the characteristics of the ak8857 internal analog band lim iting filter (anti-aliasing), which is in front of the ad converter input, are as follows: 1db (~6mhz ) ? 35db (27mhz)?.typical value analog clamp circuit ? in ak8857, the input video signal is clamping with analog circuit. the clamping method is show as follows. [cvbs signal decoding] ak8857 clamps the input signal to sync tip. (analog sync tip clamp) the clamp timing pulse, with its origin at the falling edge of the internally synchronized and separated sync signal, is generated at approximat ely the central positi on of the sync signal. [s-video signal decoding] (y signal) ak8857 clamps the y signal to sync tip. (analog sync tip clamp) the clamp timing pulse, with its origin at t he falling edge of the internally synchronized and separated sync signal, is generated at approximat ely the central positi on of the sync signal. (c signal) ak8857 clamps the c signal to the mi ddle level. (analog middle clamp) the clamp timing pulse is generated at same timing with y signal. analog middle clamp analog sync tip clamp y c analog sync tip clamp cvbs ??` -80 -70 -60 -50 -40 -30 -20 -10 0 10 0.1 1 10 100 frequency[mhz] gain[db] filter characteristic
[ AK8857VQ] ms1189-e-01 2010/12 -20- additionary, the ak8857 can change the position, width and current value of clamp pulse by registers. clpwidth[1:0]: set the width of clamp pulse. clpwidth[1:0]-bit clamp width notes [00] 296nsec [01] 593nsec [10] 1.1usec [11] 2.2usec clpstat[1:0]: set the position of clamp pulse. clpstat[1:0]-bit clamp position notes [00] sync tip/ middle/ bottom clamp: centor of horizontal sync [01] (1/128) h delay. [10] (2/128) h advance [11] (1/128) h advance the positions of all clamp pulse are changed. clpstat[1:0] = 00 clpstat[1:0] = 01 clpstat[1:0] = 11 clpstat[1:0] = 10 clamp timing pulse 2/128h advance 1/128h delay 1/128h advance clpwidth[1:0] clpg[1:0] : set the current value of fine clamp in analog block. clpg[1:0]-bit clamp current value notes [00] min. [01] middle 1 (default) [10] middle 2 [11] max. middle 1 = (min. x 3) middle 2 = (min. x 5) max. = (min. x 7) udg[1:0]: set the current value of rough clamp in analog block. udg[1:0]-bit clamp current value notes [00] min. (default) [01] middle 1 [10] middle 2 [11] max. middle 1 = (min. x 2) middle 2 = (min. x 3) max. = (min. x 4) its digital circuit clamps the digitized input data to the pedestal level (digital pedestal clamp), and will be described later.
[ AK8857VQ] ms1189-e-01 2010/12 -21- output data format setting (pixel size / progressive output) ? the ak8857 can convert the output pixel size from the original input pixel size. the ak8857 also can convert the interlaced input signal to progressive output signal. ? the ak8857 supported output fo rmat is shown below input signal output pixel size interlace / progressive output output clock notes interlace 27mhz 720x487 (itu-r bt.601) progressive 54mhz (*1) interlace 27mhz 800x480 (wvga) progressive 54mhz (*1) interlace 27mhz 640x480 (vga) progressive 54mhz (*1) 400x240 (wqvga) progressive 27mhz (*2) 320x240 (qvga) progressive 27mhz (*2) 400x234(ega) progressive 27mhz (*2) 480x240(wega1) progressive 27mhz (*2) 525 line ntsc-m, j, ntsc-4.43, pal-m, pal-60 480x234(wega2) progressive 27mhz (*2) interlace 27mhz 720x576 (itu-r bt.601) progressive 54mhz (*1) interlace 27mhz 800x480 (wvga) progressive 54mhz (*1) interlace 27mhz 640x480 (vga) progressive 54mhz (*1) 400x240 (wqvga) progressive 27mhz (*2) 320x240 (qvga) progressive 27mhz (*2) 400x234(ega) progressive 27mhz (*2) 480x240(wega1) progressive 27mhz (*2) 625 line pal-b,d,g,h,i,n, pal-nc secam 480x234(wega2) progressive 27mhz (*2) (*1) interlcae signal to progressive signal c onversion is using line repeating process. the frame rates for progressive output signal is selectable between 30frm/sec* and 60frm/sec*. (*2) only progressive output is support for this section. it?s not mentioned here, during the pixel size conver sion the data is interpolar before being generated at the output. if the input signal quality is poor, there is a case where it cannot satisfy the timing diagram shown below. example: if the input signal line is shortened than the normal, it w ill effect eav sync signal and hd signal timing for the next line and for that reas on the output signal will be effected as well. *frm/sec: frame number in 1 sec
[ AK8857VQ] ms1189-e-01 2010/12 -22- the figure below shows the rela tionship between 1-line data pixe l and sync signal timing for each output pixel size. *() in the figure below refers to clock pixels of 625-line input. *because the data is sampling to a fixed-clock, the cycle period from end of active signal to the next line of horizontal sync signal is fixed is not guarantee. 720x487, 720x576(itu-r bt.601) 244clk (264clk) 128clk 1440clk 32clk (24clk) hd dvalid hact video signal active video section 640x480(vga) 324clk (344clk) 128clk 1280clk 112clk (104clk) hd dvalid hact video signal active video section
[ AK8857VQ] ms1189-e-01 2010/12 -23- 800x480(wvga) 84clk (104clk) 128clk 1600clk 32clk (24clk) hd dvalid hact video signal active video section 320x240(qvga) 644clk (664clk) 128clk 640clk 432clk (424clk) hd dvalid hact video signal active video section 400x240(wqvga), 400x234(ega) 564clk (584clk) 128clk 800clk 352clk (344clk) hd dvalid hact video signal active video section
[ AK8857VQ] ms1189-e-01 2010/12 -24- 480x240(wega1), 480x234(wega2), 480x272 484clk (504clk) 128clk 960clk 272clk (264clk) hd dvalid hact video signal active video section relationship between sync timing of 1 frame to the next frame for each output pixel size is shown below. the timing of hd, hact, dvalid and vact signal shown in the figure is enlarge. dvalid hd hact vact video signal input v act falling edge timing vact rising edge timing
[ AK8857VQ] ms1189-e-01 2010/12 -25- input: 525-line, horizontal : 487-line, output : interlace odd even vd field 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 dvalid hd hact vact video signal even odd vd field 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 dvalid hd hact vact video signal field vd 13 14 17 18 19 20 21 22 23 24 260 dvalid hd hact vact video signal field vd 276 277 278 279 280 281 282 283 284 285 286 287 288 522 dvalid hd hact vact video signal input input input input 15 16 25
[ AK8857VQ] ms1189-e-01 2010/12 -26- input: 525-line, horizontal: 487-line, output: progressive (60frm/sec) vd field 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 dvalid hd hact vact video signal vd field 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 dvalid hd hact vact video signal field vd 13 14 15 16 17 18 19 20 21 22 23 24 25 260 dvalid hd hact vact video signal field vd 276 277 278 279 280 281 282 283 284 285 286 287 288 522 dvalid hd hact vact video signal input input input input a b c d because of line repeating process during progressive signal conversion, as shown in the figure above a line and b line / c line and d line is output as the same signal. t he field signal is being toggle. * both odd/ even field has 486-line du ring active secti on not 487-line.
[ AK8857VQ] ms1189-e-01 2010/12 -27- input : 525-line, horizontal line : 487-line, output : progressive (30frm/sec) (odd field output) vd field 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 dvalid hd hact vact video signal vd field 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 dvalid hd hact vact video signal field vd 13 14 15 16 17 18 19 20 21 22 23 24 25 260 dvalid hd hact vact video signal field vd 276 277 278 279 280 281 282 283 284 285 286 287 288 522 dvalid hd hact vact video signal input a b c d input input input because of line repeating process during progressive signal conversion, as shown in the figure above a line and b line / c line and d line is output as the same signal. t he field signal is being toggle. * both odd/ even field has 486-line du ring active secti on not 487-line.
[ AK8857VQ] ms1189-e-01 2010/12 -28- input : 525-line, horizont al line : 487-line, output : progressi ve (30frm/sec) ( even field output) vd field 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 dvalid hd hact vact video signal vd field 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 dvalid hd hact vact video signal field vd 13 14 15 16 17 18 19 20 21 22 23 24 25 260 dvalid hd hact vact video signal field vd 276 277 278 279 280 281 282 283 284 285 286 287 288 522 dvalid hd hact vact video signal input a b c d input input input because of line repeating process during progressive signal conversion, as shown in the figure above a line and b line / c line and d line is output as the same signal. t he field signal is being toggle. * both odd/ even field has 486-line du ring active secti on not 487-line.
[ AK8857VQ] ms1189-e-01 2010/12 -29- input : 525-line, horizontal li ne : 487-line, output : interlace odd even vd field 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 dvalid hd hact vact video signal even odd vd field 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 dvalid hd hact vact video signal field vd 13 14 15 16 17 18 19 20 21 22 23 24 25 260 dvalid hd hact vact video signal field vd 276 277 278 279 280 281 282 283 284 285 286 287 288 522 dvalid hd hact vact video signal input input input input
[ AK8857VQ] ms1189-e-01 2010/12 -30- input : 525-line, horizontal line : 480-li ne, output : progressive (60frm/sec) vd field 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 dvalid hd hact vact video signal vd field 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 dvalid hd hact vact video signal field vd 13 14 15 16 17 18 19 20 21 22 23 24 25 260 dvalid hd hact vact video signal field vd 276 277 278 279 280 281 282 283 284 285 286 287 288 522 dvalid hd hact vact video signal input input input input a b c d because of line repeating process during progressive signal conversion, as shown in the figure above a line and b line / c line and d line is output as the same signal. t he field signal is being toggle.
[ AK8857VQ] ms1189-e-01 2010/12 -31- input : 525-line, horizontal line : 480-line, output : progressive (30frm/sec) (odd field output) vd field 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 dvalid hd hact vact video signal vd field 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 dvalid hd hact vact video signal field vd 13 14 15 16 17 18 19 20 21 22 23 24 25 260 dvalid hd hact vact video signal field vd 276 277 278 279 280 281 282 283 284 285 286 287 288 522 dvalid hd hact vact video signal input a b c d input input input because of line repeating process during progressive signal conversion, as shown in the figure above a line and b line / c line and d line is output as the same signal. t he field signal is being toggle.
[ AK8857VQ] ms1189-e-01 2010/12 -32- input : 525-line, horizont al line : 480-line, output : progressive (30frm/sec) (even field output) vd field 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 dvalid hd hact vact video signal vd field 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 dvalid hd hact vact video signal field vd 13 14 15 16 17 18 19 20 21 22 23 24 25 260 dvalid hd hact vact video signal field vd 276 277 278 279 280 281 282 283 284 285 286 287 288 522 dvalid hd hact vact video signal input a b c d input input input because of line repeating process during progressive signal conversion, as shown in the figure above a line and b line / c line and d line is output as the same signal. t he field signal is being toggle.
[ AK8857VQ] ms1189-e-01 2010/12 -33- input : 525-line, horizontal line : 240-li ne/234-line, output : (odd field output) odd even vd field 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 dvalid hd hact vact video signal even odd vd field 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 dvalid hd hact vact video signal field vd 13 14 15 16 17 18 19 20 21 22 23 24 25 260 dvalid hd hact vact video signal field vd 276 277 278 279 280 281 282 283 284 285 286 287 288 522 dvalid hd hact vact video signal input input input input in 234-line output case, as shown above lines from line 22 to 24 and from line 259 to 261 is not count as active line. for that reason, hact, vact and dvalid is ?high? during the line mentioned above.
[ AK8857VQ] ms1189-e-01 2010/12 -34- input : 525-line, horizontal line : 240-li ne/234-line, output : (even field output) odd even vd field 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 dvalid hd hact vact video signal even odd vd field 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 dvalid hd hact vact video signal field vd 13 14 15 16 17 18 19 20 21 22 23 24 25 260 dvalid hd hact vact video signal field vd 276 277 278 279 280 281 282 283 284 285 286 287 288 522 dvalid hd hact vact video signal input input input input in 234-line output case, as shown above lines from line 22 to 24 and from line 259 to 261 is not count as active line. for that reason, hact, vact and dvalid is ?high? during the line mentioned above.
[ AK8857VQ] ms1189-e-01 2010/12 -35- input : 625-line, hori zontal line : 576-line even odd vd field 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 dvalid hd hact vact video signal odd even vd field 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 dvalid hd hact vact video signal field vd 10 21 22 23 24 25 26 27 28 29 30 31 306 dvalid hd hact vact video signal field vd 322 277 334 335 336 337 338 339 340 341 342 343 344 619 dvalid hd hact vact video signal input input input input
[ AK8857VQ] ms1189-e-01 2010/12 -36- input : 625-line, horizontal line : 576-li ne, output : progressive (60frm/sec) vd field 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 dvalid hd hact vact video signal vd field 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 dvalid hd hact vact video signal field vd 10 21 22 23 24 25 26 27 28 29 30 31 306 dvalid hd hact vact video signal field vd 322 277 334 335 336 337 338 339 340 341 342 343 344 619 dvalid hd hact vact video signal a b c d input input input input because of line repeating process during progressive signal conversion, as shown in the figure above a line and b line / c line and d line is output as the same signal. t he field signal is being toggle. * in the above figure, both odd/even field line number is 574-line. to set the active li ne to 576-line, set the vbil[2:0] register to 0x01 value.
[ AK8857VQ] ms1189-e-01 2010/12 -37- input : 625-line, horizontal line : 576-line, output : progressive (30frm/sec) (odd field output) vd field 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 dvalid hd hact vact video signal vd field 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 dvalid hd hact vact video signal field vd 10 21 22 23 24 25 26 27 28 29 30 31 306 dvalid hd hact vact video signal field vd 322 277 334 335 336 337 338 339 340 341 342 343 344 619 dvalid hd hact vact video signal a b c d input input input input because of line repeating process during progressive signal conversion, as shown in the figure above a line and b line / c line and d line is output as the same signal. t he field signal is being toggle. * in the above figure, both odd/even field line number is 574-line. to set the active line to 576-line, set the vbil[2:0] register to 0x01 value.
[ AK8857VQ] ms1189-e-01 2010/12 -38- input : 625-line, horizont al line : 576-line, output : progressive (30frm/sec) (even field output) vd field 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 dvalid hd hact vact video signal vd field 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 dvalid hd hact vact video signal field vd 10 21 22 23 24 25 26 27 28 29 30 31 306 dvalid hd hact vact video signal field vd 322 277 334 335 336 337 338 339 340 341 342 343 344 619 dvalid hd hact vact video signal a b c d input input input input because of line repeating process during progressive signal conversion, as shown in the figure above a line and b line / c line and d line is output as the same signal. t he field signal is being toggle. * in the above figure, both odd/even field line number is 574-line. to set the active line to 576-line, set the vbil[2:0] register to 0x01 value.
[ AK8857VQ] ms1189-e-01 2010/12 -39- input : 625-line, hori zontal line : 480-line even odd vd field 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 dvalid hd hact vact video signal odd even vd field 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 dvalid hd hact vact video signal field vd 10 21 22 23 24 25 26 27 28 29 30 31 306 dvalid hd hact vact video signal field vd 322 277 334 335 336 337 338 339 340 341 342 343 344 619 dvalid hd hact vact video signal input input input input as shown in the figure above, start from line 25 / li ne 338 to the next starting line of each 5 line, the line is output as not active line. hact and dv alid is ?high? during the line mentioned. eav sync code is added to the line ment ioned above and sav sync code is not.
[ AK8857VQ] ms1189-e-01 2010/12 -40- input : 625-line, horizontal line : 480-li ne, output : progressive (60frm/sec) vd field 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 dvalid hd hact vact video signal vd field 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 dvalid hd hact vact video signal field vd 10 21 22 23 24 25 26 27 28 29 30 31 306 dvalid hd hact vact video signal field vd 322 277 334 335 336 337 338 339 340 341 342 343 344 619 dvalid hd hact vact video signal a b c d input input input input because of line repeating process during progressive signal conversion, as shown in the figure above a line and b line / c line and d line is output as the same signal. t he field signal is being toggle. as shown in the figure above, start from line 25 / line 338 to the next starting line of each 10 line, the line is output as not active line. hact and dvalid is ?high? during the line mentioned. eav sync code is added to the line m entioned above and sav sync code is not. * in the above figure, both odd/even field line number is 478-line. to set the active li ne to 480-line, set the vbil[2:0] register value to 0x01.
[ AK8857VQ] ms1189-e-01 2010/12 -41- input : 625-line, horizontal line : 480-line, output : progressive (30frm/sec) (odd field output) vd field 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 dvalid hd hact vact video signal vd field 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 dvalid hd hact vact video signal field vd 10 21 22 23 24 25 26 27 28 29 30 31 306 dvalid hd hact vact video signal field vd 322 277 334 335 336 337 338 339 340 341 342 343 344 619 dvalid hd hact vact video signal a b c d input input input input because of line repeating process during progressive signal conversion, as s hown in the above figure a line and b line / c line and d line is output as the same signal. t he field signal is being toggle. as shown in the figure above, start from line 25 to the next starting line of each 10 line, the line is output as not active line. hact and dval id is ?high? during the line mentioned. eav sync code is added to the line m entioned above and sav sync code is not. * in the above figure, both odd/even field line number is 478-line. to set the active line to 480-line, set the vbil[2:0] register value to 0x01.
[ AK8857VQ] ms1189-e-01 2010/12 -42- input : 625-line, horizont al line : 480-line, output : progressive (30frm/sec) (even field output) vd field 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 dvalid hd hact vact video signal vd field 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 dvalid hd hact vact video signal field vd 10 21 22 23 24 25 26 27 28 29 30 31 306 dvalid hd hact vact video signal field vd 322 277 334 335 336 337 338 339 340 341 342 343 344 619 dvalid hd hact vact video signal a b c d input input input input because of line repeating process dur ing progressive signal conversion, as shown in the figure above, a line and b line / c line and d line is output as the same signal. t he field signal is being toggle. as shown in the figure above, start from line 338 to the next starting line of each 10 line, the line is output as not active line. hact and dval id is ?high? during the line mentioned. eav sync code is added to the line m entioned above and sav sync code is not. * in the above figure, both odd/even field line number is 478-line. to set the active li ne to 480-line, set the vbil[2:0] register value to 0x01.
[ AK8857VQ] ms1189-e-01 2010/12 -43- input : 625-line, horizontal line : 240-line/234-lin e, output : progressive (odd field output) even odd vd field 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 dvalid hd hact vact video signal odd even vd field 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 dvalid hd hact vact video signal field vd 10 21 22 23 24 25 26 27 28 29 30 31 306 dvalid hd hact vact video signal field vd 322 277 334 335 336 337 338 339 340 341 342 343 344 619 dvalid hd hact vact video signal input input input input as shown in the figure above, start from line 25 to t he next starting line of each 5 line, the line is output as not active line. hact and dvalid is ?high? during the line mentioned. eav sync code is added to the line m entioned above and sav sync code is not. in 234-line output case, as shown above, lines from line 23 to 26 and from line 308 to 310 is not count as active line. for that reason, hact, vact and dvalid output is ?high? during the line mentioned above.
[ AK8857VQ] ms1189-e-01 2010/12 -44- input : 625-line, horizontal li ne : 240-line/234-line, output : pr ogressive (even field output) even odd vd field 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 dvalid hd hact vact video signal odd even vd field 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 dvalid hd hact vact video signal field vd 10 21 22 23 24 25 26 27 28 29 30 31 306 dvalid hd hact vact video signal field vd 322 277 334 335 336 337 338 339 340 341 342 343 344 619 dvalid hd hact vact video signal input input input input as shown in the figure above, start from line 338 to the next starting line of each 5 line, the line is output as not active line. hact and dval id is ?high? during the line mentioned. eav sync code is added to the line m entioned above and sav sync code is not. in 234-line output case, as shown above, lines from line 336 to 339 and from line 621 to 623 is not count as active line. for that reason, hact, vact and dvalid output is ?high? during the line mentioned above.
[ AK8857VQ] ms1189-e-01 2010/12 -45- input video signal categorization the ak8857 can decode the following video signals, in accordance with the register setting. ntsc-m,j ntsc-4.43 pal-b,d,g,h,i,n pal-nc pal-m pal-60 secam the register settings for the input signal c haracterization are essentially as follows. vscf[1:0]-bi: setting for subca rrier frequency of input signal vscf[1:0]-bit subcarrier frequency (mhz) notes [00] 3.57954545 ntsc-m,j [01] 3.57561149 pal-m [10] 3.58205625 pal-nc [11] 4.43361875 pal-b,d,g,h,i,n , ntsc-4.43 , pal-60 secam* *for secam input signal, set vscf[1:0] to [11]. vcen[1:0]-bit: setting for color encode format of input signal. vcen[1:0]-bit color encode format notes [00] ntsc [01] pal [10] secam [11] reserved vlf-bit : setting for line fr equency of each input frame. vlf-bit number of lines notes [0] 525 ntsc-m,j , ntsc-4.43 , pal-m, pal-60 [1] 625 pal-b,d,g,h,i,n,nc , secam bw-bit: setting for decoding of input signal as monochrome signal (monochrome mode) bw-bit signal type notes [0] not monochrome (monochrome mode off) [1] decode as monochrome si gnal (monochrome mode on) in the monochrome mode at cvbs decoding, the input signal is treated as a monochrome signal, and all sampling data digitized the the ad converter passe s through the luminance process and is processed as a luminance signal. thus, with this bit on, the signal input to the y/c separation block is all output as luminance signal data to the lumi nance signal processing block. in the monochrome mode at s-vi deo decoding, y signal is only decoded. in the monochrome mode, the cbcr code is output as 0x80 (601 level data) regardless of the input.
[ AK8857VQ] ms1189-e-01 2010/12 -46- setup-bit: setting for presence or absence of input signal setup. setup-bit setup presence/absence notes [0] setup absent [1] setup present 7.5ire setup with the setup present setting, the luminance and color signals are processed as follows: luminance signal: y=(y-7.5)/0.925 color signal: u=u/0.925, v=v/0.925
[ AK8857VQ] ms1189-e-01 2010/12 -47- input signal auto detection function the register settings for auto detection are essentially as follows. autodet-bit: settings for auto detection of input signal (auto detection mode) autodet-bit auto detection notes [0] off manual setting [1] on the auto detection recognizes the following parameters. number of lines per frame: 525/625 carrier frequencies: 3.57954545 3.57561149 3.58205625 4.43361875 color encoding formats: ntsc pal secam monochrome signal: not monochrome/monochrome note: automatic monochrome detection is active if the color kill se tting is on (colkill-bit = [1].) the ak8857 stores the detected parameter to the i nput video status register (thus, as an internal notice function). this enables the host to distinguish among the formats ntsc-m, j; ntsc-4.43; pal-b, d, g, h, i, n; pal-m; pal-nc; pal-60; secam; and monochrome. it should be noted that it does not detect ntsc-m, nt sc-j, or pal-b, d, g, h, i, n formats. (notice) ?direct sync vlock? (sub-address0x03[7]=1) must not use when it is being operated on auto detection function.
[ AK8857VQ] ms1189-e-01 2010/12 -48- limiting auto input video signal detection function the ak8857 has the function to limit the input video signal to be detected during auto detection mode. ndmode register: for limiting auto detection candidates bit register name r/w definition bit 0 ndpalm no detect pal-m bit r/w [0]: pal-m candidate [1]: pal-m non-candidate bit 1 ndpalnc no detect pal-nc bit r/w 0]: pal-nc candidate [1]: pal-nc non-candidate bit 2 ndsecam no detect secam bit r/w [0]: secam candidate [1]: secam non-candidate bit 3 reserved reserved r/w reserved bit 4 ndntsc443 no detect ntsc-4.43 bit r/w 0]: ntsc-4.43 candidate [1]: ntsc-4.43 non-candidate bit 5 ndpal60 no detect pal-60 bit r/w [0]: pal-60 candidate [1]: pal-60 non-candidate bit 6 nd525l no detect 525line bit r/w [0]: 525 line candidate [1]: 525 line non-candidate bit 7 nd625l no detect 625line bit r/w [0]: 625 line candidate [1]: 625 line non-candidate in making the above register settings, the following restrictions is apply, 1. setting both ndntsc443(bit 4) and ndpa l60(bit 5) to [1] (high) is prohibited. 2. setting both nd525l(bit 6) and nd625l( bit 7) to [1] (high) is prohibited. 3. to limit candidate formats, it is necessary to have the auto detection mode off while first setting the register to non-limited signal st atus and next the ndmode settings, and then setting the auto detection mode to on. set auto detection mode to off set input video standard register to non-limited signal status enter ndmode register settings set auto detection mode to on
[ AK8857VQ] ms1189-e-01 2010/12 -49- output data format in the ak8857, the settings for the output code and the vertical blanking intervals for the output signal are as follows. 601limit-bit: settings for output data code min/max 601limit-bit output data code min~max notes [0] y: 1~254 cb, cr: 1~254 default [1] y: 16~235 cb, cr: 16~240 all internal calculating operations are made with min = 1, max = 254. with 601limit-bit set to [1], codes 1~15 and 236~254 are respectively clipped to 16,235. trsvsel-bit: settings for v-bit handling in itu-r bt.656 format 525-line 625-line trsvsel-bit v-bit=0 v-bit=1 v-bit=0 v-bit=1 [0] itu-r bt 656-3 line10~line263 line273~line525 line1~line9 line264~line272 [1] itu-r bt 656-4 smpte125m line20~line263 line283~line525 line1~line19 line264~line282 line23~line310 line336~line623 line1~line22 line311~line335 line624~line625 the trsvsel register only available during the in terlace output decode by itu-r bt.601 output size. these values are unaffected by the vbil[2:0]-bits setting. vbil[2:0]-bit: settings for vertical blanking interval vbil[2:0]-bit line adjustment width notes [000] default 1line advance *1 [001] 2line advance *2 2lines advance *1 [010] 4lines advance *2 3lines advance *1 [011] 6lines advance *2 4lines advance *1 [100] 8lines advance *2 5lines advance *1 [101] 10lines advance *2 6lines advance *1 [110] 12lines advance *2 7lines advance *1 [111] 14lines advance *2 *1: other than progressive output *2: progressive output the starting position of hact signal and dval id signal is changed according to vact signal starting position.
[ AK8857VQ] ms1189-e-01 2010/12 -50- 18 19 20 21 22 23 24 25 dvalid hd hact vact video signal input dvalid hact vact vbil=[001] vbil=[000] *1 18 19 20 21 22 23 24 25 dvalid hd hact vact video signal input dvalid hact vact vbil=[001] vbil=[000] *2 sllvl-bit: settings for slice level sllvl-bit slice level [0] 25ire [1] 50ire the results of vbi slicing by the ak8857 slicing f unction are output as itu-r bt.601 digital data. the vbi interval is set via vbil[2:0]-bits. vbi slici ng is performed in the luminance signal processing path, so that the cb/cr value of the effective line 601 output code is output at the same level as the corresponding luminance signal. the slice level and the output code are set via the register. the output code value is set via the hi/low slice data set register, as follows. hi slice data set register*: setting for higher of two values resulting from slicing. default: 0xeb(235) low slice data set register*: setting for lowe r of two values resulting from slicing. default: 0x10(16) *note that a setting of 0x00 or 0xff corresponds to a special 601 code.
[ AK8857VQ] ms1189-e-01 2010/12 -51- vbidec[1:0]-bit: settings for decode data in the vbi period vbidec[1:0]-bit decode data notes [00] black level output y = 0x10 cb/cr = 0x80 [01] monochrome mode y = data converted to 601 level cb/cr = 0x80 [10] sliced data output during vbi y/cb/cr = value corresponding to slice level (value set at hi/low slice data set register) [11] reserved reserved note that, with vbi period settings of lines 1~9 and 263.5~272.5 in the 525 line and lines 623.5~6.5 and 311~318 in the 625 line, the setting vbidec[1:0] w ill not be entered and t he output will be in black level code. (mv*) ntsc/pal 601 code 714/700 235 357/350 180/175 *threshold values (mv) are approximate. 127 63 100% white 50ire threshold with setting sllvl = [1] 25ire threshold with setting sllvl = [0] ```` l l l ```` l l h h h h cb/y cr/y `````` cb/y `````` cr/y l: h: value set by high slice data set register value set by low slice data set re g iste r ````` ``````` high/low conversion is performed for either the cb /y or the cr/y combination. the above figure is an example of the conversion points for cb/y.
[ AK8857VQ] ms1189-e-01 2010/12 -52- output pin status for normal operation, the output from the data_a[7:0], hd_act_a, vd_act_a, dvalid_a, field_a, nsig_a, data_b[7:0], hd_act_b, vd_act_b, dvalid_b, field_b, nsig_b pins can each be fixed at low via the output control register. the black level and blue level output have the priority to be output from the data_a[7:0] and data_b[7:0] pins regardless of these register settings. note, however, that the oe_a, oe_b, pdn, rstn pins and ainsel[4:0] (non decode) states will have priority regardless of these register settings. output pin timing signal the timing signal can be output from the hd _act_a, vd_act_a, dvalid_a, field_a, hd_act_b, vd_act_b, dvalid_b, field_b pins. t he polarity of each timing signal at the output pin can be invert by register setting. at the hd_act output pin, the output signal c an be selected between hd signal and hact signal by register setting. at the vd_act output pin, the output signal can be selected between vd signal and vact signal by register setting. vdactsel-bit : vd/ vact signal output setting vdactsel-bit vd_act output pin setting [0] vd signal is output [1] vact signal is output hdactsel-bit : hd/ hact signal output setting hdactsel-bit hd_act output pin setting [0] hd signal is output [1] hact signal is output the polarity of output from the data_a[7:0] / data_b[7:0] and dtclkcan be inverted. clkinv-bit: dtclk signal polarity setting clkinv-bit polarity setting [0] rising edge [1] falling edge if each of a or b output 54mhz, dtclk pin output 54m hz. so, not ip conversion data is alternated by 2clk.
[ AK8857VQ] ms1189-e-01 2010/12 -53- clkinv-bit a and b block at 27mhz/54mhz output a block : ip conversion output a block : clkinv=[0] b block : clkinv=[0] d0 d1 d2 d3 d4 data_a[7:0] data_b[7:0] dtclk d0 d1 d2 d3 d4 data_a[7:0] data_b[7:0] dtclk d0 d1 d2 d3 d4 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 a block : clkinv=[1] b block : clkinv=[0] d0 d1 d2 d3 data_a[7:0] data_b[7:0] dtclk d0 d1 d2 d3 d4 data_a[7:0] data_b[7:0] dtclk d0 d1 d2 d3 d4 d0 d1 d2 d3 d4 d5 d6 d7 d8 a block : clkinv=[0] b block : clkinv=[1] data_a[7:0] data_b[7:0] dtclk d0 d1 d2 d3 d4 d0 d1 d2 d3 data_a[7:0] data_b[7:0] dtclk d0 d1 d2 d3 d4 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 a block : clkinv=[1] b block : clkinv=[1] data_a[7:0] data_b[7:0] dtclk d0 d1 d2 d3 d0 d1 d2 d3 data_a[7:0] data_b[7:0] dtclk d0 d1 d2 d3 d4 d0 d1 d2 d3 d4 d5 d6 d7 d8 output data timing the ak8857 can control timing of output data. ycdelay[2:0]-bit: adjustment of y and c timing. ycdelay[2:0]-bit y and c timing notes [001] y advance 1sample to ward c. 2clk advance [010] y advance 2 sample toward c. 4clk advance [011] y advance 3 sample toward c. 6clk advance [000] no delay and advance. default value [101] y delay 3 sample toward c. 6clk delay [110] y delay 2 sample toward c. 4clk delay [111] y delay 1 sample toward c. 2clk delay [100] reserved *setting by 2 complement because each sample is delay/advance toward c, 1sample is equall to 1clk width. dtclk cb0 y0 cr0 y1 cb1 y2 cr1 y3 cb2 y4 cr2 y5 cb0 y857 cr0 y0 cb1 y1 cr1 y2 cb2 y3 cr2 y4 cb0 y1 cr0 y2 cb1 y3 cr1 y4 cb2 y5 cr2 y6 ycdelay[2:0] = [001] ycdelay[2:0] = [111] y/c default 1sample delay 1sample adv. ycdelay[2:0] = [000]
[ AK8857VQ] ms1189-e-01 2010/12 -54- actsta[2:0]-bit: adjustment of active video start position actsta[2:0]-bit line and active video start notes [001] 525 line starting postion is delay 1 sample 2clk delay [010] 525 line starting postion is delay 2 sample 4clk delay [011] 525 line starting postion is delay 3 sample 6clk delay [000] 525 line default value normal position [101] 525 line starting postion is advance 3 sample 6clk advance [110] 525 line starting postion is advance 2 sample 4clk advance [111] 525 line starting postion is advance 1 sample 2clk advance [100] reserved reserved when the start position of acti ve video is changed, the end positi on of active video also changed. (active video space is fixed) ?? example : 720x487, 720x576(itu-r bt.601) 244clk (264clk) 128clk 1440clk 32clk (24clk) hd dvalid hact video signal active video section dvalid hact 1sample (2clk) 1sample (2clk) a ctsta[2:0] =[000] a ctsta[2:0] =[001] vlock mechanism the ak8857 synchronizes internal op eration with the input signal fram e structure. if, for example, the frame structure of the input si gnal comprises 524 lines, the internal operation will ha ve a structure of 524 lines per frame. this mechanism is termed the vlock mechanism. if an input signal changes from a structure of 525 lines per frame to one of 524 lines per frame, internal operation will change accordingly, and the vlock mechanism will go to unlock via a pull-in process. in such case, the unlock status can be confirmed via the control register [vlock-bi t]. note that the time required for locking of the vlock mechani sm upon channel or ot her input signal switching will be about 2 frames. (pll sync vlock)
[ AK8857VQ] ms1189-e-01 2010/12 -55- additionary, ak8857 supports ?direct locking? mode t hat is not using vlock operation. (direct sync vlock) vlocksel-bit internal operation with the input signal frame structure [0] pll sync vlock [1] direct sync vlock (notice) ?auto detection function? (sub-address0x0e[7]=1, 0x 26[7]=1) must not use when it is being operated on direct sync vlock. auto gain control_agc the agc of the ak8857 measures the size of the i nput sync signal (i.e., t he difference between the sync tip and pedestal levels), and adjusts the pga value to bring the sync signal level to 286 a or 300 b mv. the agc function amplifies the input signal to the appropriate size and enables input to the ad converter. the agc function in the ak8857 is adaptiv e, and thus includes peak agc as well as sync agc. peak agc is effective for input signals in which t he sync signal level is appr opriate and only the active video signal is large. a ntsc-m, j; ntsc-4.43; pal-m??????????..286mv b pal-b, d, g, h, i, n; pal-nc; pal-60; secam????300mv agct[1:0]-bit : settings for agc time constant agct[1:0]-bit time constant notes [00] disable agc off, pga register enabled. [01] fast t= 1field [10] middle t= 7fields [11] slow t= 29fields t is the time constant. manual setting of the pga register is possible only if agc is disabled. agcc-bit : settings for agc non-sensing range agcc[1:0]-bit non-sensing range notes [00] 2lsb [01] 3lsb [10] 4lsb [11] none agcfrz-bit : settings for freezing agc function agcfrz-bit agc status notes [0] non-frozen [1] frozen note. the gain value at the time of freezing is maintained during the frozen state, and it is then possible to read out the gain value via the pga1,2 control register.
[ AK8857VQ] ms1189-e-01 2010/12 -56- agctl-bit : settings for selection of quick or slow transition between peak and sync agc agctl-bit agc transition notes [0] quick [1] slow auto color control (acc) the acc of the ak8854 measures the level of the i nput signal color burst, and adjusts the level to 286 or 300 mv, as appropriate. the acc is not applicable to secam input. as in agc, both acc time constant a nd acc freeze settings can be entered. ntsc-m,j , ntsc-4.43 , pal-m??????????..286mv pal-b,d,g,h,i,n , pal-nc , pal-60????. 300mv acct[1:0]-bit : settings for acc time constant acct[1:0]-bit time constant notes [00] disable acc off [01] fast t= 2fields [10] middle t= 8fields [11] slow t= 30fields accfrz-bit : settings for freezing acc function accfrz-bit acc status notes [0] non-frozen [1] frozen the acc and color saturation functions operat e independently. if acc is enabled, the color saturation adjustment is applied to the signal that has been adjusted to the appropriate level by the acc. no-signal output if no input signal is found (as shown by the control bi t nosig-bit), the output signal is black-level, blue level (blueback), or input-state (sandsto rm), depending on the register setting. nsigmd-bit : settings for output signals for no input signal nsigmd [1:0]-bit output notes [00] black-level [01] blue-level (blueback) [10] input-state (sandstorm) [11] reserved
[ AK8857VQ] ms1189-e-01 2010/12 -57- y/c separation the adaptive two-dimensional y/c separation of the ak8857 utilizes a correlati on detector to select the best-correlated direction from among vertical , horizontal, and diagonal samples, and selects the optimum y/c separation mode. for ntsc-4.43, pal-60, and secam inputs, the y/c separation is one-dimensional only, regardless of the setting. ycsep[1:0]-bit : settings for y/c separation method ycsep[1:0]-bit y/c separation mode notes [00] adaptive [01] 1-d 1d (bpf) [10] 2-d ntsc-m, j, pal-m: 3 line 2-d pal-b, d, g, h, i, n, nc: 5 line 2-d ??? (*1) [11] reserved for ntsc-4.43, pal-60, and secam inputs, y/c separation is 1-d only, regardless of the setting. c filter the bandwidth of the c filter can be set via the register, as follows. c358fil[1:0]: settings for c filter bandwidth, fo r input signal with 3.58 mhz subcarrier wave c358fil[1:0] -bit c filter bandwidth setting notes [00] narrow [01] medium [10] wide [11] reserved ntsc-m, j, pal-m, pal-nc
[ AK8857VQ] ms1189-e-01 2010/12 -58- c443fil[1:0]: settings for c filter bandwidth, fo r input signal with 4.43 mhz subcarrier wave c443fil[1:0] -bit c filter bandwidth setting notes [00] narrow [01] medium [10] wide [11] reserved pal-b,d,g,h,i,n , ntsc-4.43 , pal-60 note. no bandwidth selection is possible for secam input. uv filter the uv bandwidth can be changed by switch between low pass filters types for the demodulated c signal. ? uvfilsel-bit : settings for uv filt er switching (cvbs or s-video input) uvfilsel?bit bandwidth notes [0] wide [1] narrow digital pixel interpolator the digital pixel interpolator of the ak8857 aligns ve rtical pixel positions and it also aligns horizontal pixel position in fixed-clock operating modes. intpoloff-bit : settings for pixel interpolator operation intpoloff-bit interpolator operation notes [0] on [1] off
[ AK8857VQ] ms1189-e-01 2010/12 -59- clock the ak8857 is operational by fixed-clock. to sy nchronized analog video sig nal, it doesn?t have pll internally. the input clock is 27mhz. only when progressive output of 720x487, vga, wvga output format, the data is sampling to 54mhz generated internally from the input clock 27mhz. phase correction in pal-b, d, g, h, i, n, nc, 60, and m decoding, the ak8857 performs phase correction for each line. with this function on, color averaging is perfo rmed for each line. in the adaptive phase correction mode, interline phase correlation is sampled and colo r averaging is performed for correlated samples. interline color averaging is also performed in ntsc-m and j decoding. no phase correction or color averagi ng is performed in secam decoding. dpal[1:0]-bit : settings for phase correction dpal[1:0]-bit status notes [00] adaptive phase correction mode [01] phase correction on [10] phase correction off [11] reserved output interface [1] interface with eav/sav sync the eav/sav sync code of itu-r bt.656 standard interface can be added to the output data of ak8857 when itu-r bt.601 output size interlaced format is selected. for the output size other than itu-r bt.601 output size format, 2 pixels is added to the eav/sav sync code at the outside of dvalid signal active section. the changes also apply to v bit and fbit according to the lines where the polarity of vact signal and field signal is changed. dvalid hd hact vact eav relation between vact and v bi t v bit eav sav even odd odd even vd field hd dvalid eav sav sav f bit eav relation between field and f bit
[ AK8857VQ] ms1189-e-01 2010/12 -60- data [7:0] dvalid hd dtclk cb0y0 cr0 y1cb1y2 cr1 sav 00 00 ff eav 00 00 ff realtion between dvalid and eav/sav sync since the ak8857 data is sampling us ing fixed-clock, the sample number from eav to sav is not guarantee. for that reason, the default data output is in sav format. eavsav-bit : eav/sav sync code is superimposed to the output data setting. eavsav-bit status notes [0] add default value [1] no change [2] interface with timing signal the ak8857 can output the hd signal, vd signal, hact signal, vact sign al, dvalid signal and field signal at the output pins. pleas e refer to the output data format setting for the correct timing of each signal. the space between dvalid signal is changed from low to high, and hd/hact signals is changed from high to low is not guarantee and for that r eason the sample number for 1 line also is not guarantee. but the space between hd/hact signals is changed from high to low and dvalid signal is changed from low to high, the timing is fixed. 244clk (264clk) 128clk 1440clk 32clk (24clk) hd dvalid hact video signal active video portion fixed s p ace not fixed cb0 cr0 y0 y1 cb1 y2 cr1 y3 y719 cr359 y718 ff sav
[ AK8857VQ] ms1189-e-01 2010/12 -61- automatic setup processing in auto detection mode, the ak8857 can perform automatic setup processing in accordance with the detected signal. setup processing of the signal to be decoded consists of the following. luminance signal: y=(y-7.5)/0.925 color signal: u=u/0.925, v=v/0.925 automatic setup processing (ak8857 in auto detection mode) register setting detected signal setup-bit stupatoff-bit (automatic setup processing) detected signal setup processing status [0] disable [0] [1] disable [0] enable ntsc-m,j pal-b,d,g,h,i,n pal-nc , 60 secam [1] [1] enable [0] enable [0] [1] disable [0] enable pal-m ntsc-4.43 [1] [1] enable in the auto detection mode, the se tup processing status will be determi ned by the regi ster setting on the basis of the detected signal ca tegory, with no detection as to the presence or absence of input signal setup. pga (programmable gain amp) the ak8857 digital pga is buit internally. the setting value can be set in range of ? 3db to 10db using adc output data. the register default setting is 0x1f (=0db). when analog video signal (0.5vpp) is input to ain ch, the setting value becomes the default value. g pga gain(db) pga pga register setting(dec.) pga1[7:0]-bit : sets the pga value. pga2[7:0]-bit : sets the pga value. cvbs input : pga1 is enable for a block data out put and pga2 is enable for b block data output. s-video input : pga1 is enable for luminance signal and pga2 is enable for color signal. notes : if the output of a block and b block are selected from the same ain ch, only pga1 setting is valid and pga2 is not valid. this register can read the agc setting value. if agc is enabled, the pga[7:0]-bits setting value has no effect, and the pga setting can be manually entered in the register only if agc is disabled. signal input to the ak8857 should be made with the input level attenuated approximately 39% (-8.19 db) by resistance splitting. () {} ? ? ? ? ? ? ? ? = 625 . 0 31 006 . 0 625 . 0 log 20 pga g
[ AK8857VQ] ms1189-e-01 2010/12 -62- sync separation, sync detecti on, and black-level fine tuning the ak8857 performs sync separation and sync detec tion on the digitized i nput signal, uses the detected sync signal as the timing reference for the decoding process, and calculates the phase error from the separated sync signal and applies it to cont rol of the sampling clock. black-level tuning can be performed in the sync separation block. the blac k-level fine-tuning band, which is 10 bits wide before rec 601 conversion, can be adjusted -8~+7 lsb in 1-lsb steps, with one step resulting in a change of about 0.4 lsb in the output code bklvl[3:0]-bit : settings for black-level fine tuning bklvl[3:0]-bit code adjustment of black level approx. change in 601 level (lsb) [0001] +1 +0.4 [0010] +2 +0.8 [0011] +3 +1.2 [0100] +4 +1.6 [0101] +5 +2.0 [0110] +6 +2.4 [0111] +7 +2.8 [0000] default none [1000] -8 -3.2 [1001] -7 -2.8 [1010] -6 -2.4 [1011] -5 -2.0 [1100] -4 -1.6 [1101] -3 -1.2 [1110] -2 -0.8 [1111] -1 -0.4 the black level is adjusted upward or downward by the value of the setting, which must be in 2?s-complement form. black-level adjustment is al so enabled during the vert ical blanking interval. digital pedestal clamp the digitally converted input signal is clamped in the digital signal pr ocessing block. the internal clamp position depends on the input signal type (either 286 mv sync or 300 mv sync), but pedestal position is output as code 16 for both types. the digital pedestal clamp function can adjust the time constant and set the coring level. dpct[1:0]-bit : settings for digi tal pedestal clamp time constant dpct[1:0]-bit transition time constant notes [00] fast [01] middle [10] slow [11] disable digita l pedestal clamp off dpcc[1:0]-bit : settings for digital clamp pedestal coring level dpcc[1:0]-bit transition time constant (bit) notes [00] 1bit [01] 2bit [10] 3bit [11] non-coring
[ AK8857VQ] ms1189-e-01 2010/12 -63- color killer in cvbs or s-video input, the chroma signal quality of the input signal is determined by comparison of its color burst level against the thres hold setting in the color killer control register. if the level is below the threshold, the color killer is activated, resulting in processing of the input as a monochrome signal and thus with cbcr data fi xed at 0x80. depending on the register setting, the color killer may also be activated by failure of the color decode pll lock. colkill-bit: settings for color killer on and off colkill-bit notes [0] enable [1] disable cklvl[3:0]-bit: for threshold setting; default setting [1000] = ? 23db. ckscm[1:0]-bit: used for thres hold setting with secam input ckscm [1:0] notes [00] {cklvl [3:0]} [01] {0, cklvl [3:1]} 1bit shift to right [10] {0,0, cklvl [3:2]} 2bit shift to right [11] reserved ckilsel: settings for co lor killer activation ckilsel-bit condition for activation notes [0] burst level below threshold setting in cklvl[3:0]-bits [1] burst level below threshold setting in cklvl[3:0]-bits, or failure of color decode pll lock * * pll lock for color decode is not activate durin g secam signal is decode. the color killer on/off status also depends on no-signal and burst-level judgement and will not effect by ckilsel setting.
[ AK8857VQ] ms1189-e-01 2010/12 -64- image quality adjustments image quality adjustments consist of contrast, br ightness, sharpness, color saturation, and hue adjustment. all image quality adjustments are dis abled during the vertical blanking interval, but contrast and brightness adjustment can be enabled by the register setting. 1. contrast adjustment cont[7:0]-bits: for contrast adjustment; default value 0x80 (no adjustment) contrast adjustment involves multiplication by the gain factor setting in this register. the equation of the multiplication can be modi fied by register setting as follows. if contsel = [0], then yout = (cont/128) x (yin ? 128) + 128 if contsel = [1], then yout = (cont/128) x yin yout: contrast obtained by the calculation yin: contrast before the calculation cont: contrast gain factor (register setting value) the gain factor can be set in the range 0~255. if the calculated value is outside the specified contrast range, it is clipped to the upper ?254? or lower ?1? limit. with a control bit 601limit setting of [1], the output w ill be in the range 16~235. contsel-bit : settings for contrast adjustment inclination contsel -bit inclination notes [0] toward luminance of 128 [1] toward luminance of 0 2. brightness adjustment br[7:0]-bits: for brightness adjustment; settings in 2?s complement; default value 0x00 (no adjustment) brightness adjustment involves multiplication of the 8bit data luminance signal, after itu-r bt.601 conversion, by the gain factor setti ng in this register, as follows. yout = yin + br yout: brightness obtained by the calculation yin: brightness before the calculation br: brightness gain factor (register setting value) the gain factor can be set in the range -127 to +127 in steps of 1, by 2?s complement entry. if the calculated value is outside the spec ified contrast range, it is clipped to the upper ?254? or lower ?1? limit. with a control bit 601limit setting of [1], the output will be in the range 16~235. 3. color saturation adjustment sat[7:0]-bits: for color saturation adjustment; default value 0x80 (no adjustment) saturation adjustment involves multiplication of the color signal by the gain factor setting in this register. the calculated result is u/v demodulated. the gain factor can be set in the range 0 to 255/128, in steps of 1/128.
[ AK8857VQ] ms1189-e-01 2010/12 -65- 4. hue adjustment hue[7:0]-bits: for hue adjustment; settings in 2? s complement; default value 0x00 (no adjustment) the ak8854 can perform hue rotation with a phase ro tation range of 45 in steps of about 0.35. 5. sharpness adjustment sharpness adjustment is performed on the lumi nance signal as shown in the following process diagram. the filter characteristics and the cori ng level can be selected by following register. a sharp image can be obtained by selection of the fi lter with the appropriate characteristics. filter coring delay luminance signal before processing sharp[1:0]-bits shcore[1:0]-bits luminance signal after processing sharp[1:0]-bit: settings for filter characteristics selection sharp[1:0]-bit filter characteristics notes [00] no filtering filter disabled [01] min [10] middle [11] max shcore[1:0]-bit : settings for coring level after sharpness filtering shcore[1:0]-bit coring level (lsb) notes [00] no coring [01] 1lsb [10] 2lsb [11] 3lsb settings apply only to filtered signal. vbiimgctl-bit: settings for brightness and contrast adjustment status (on/off) during vbi vbiimgctl -bit status during vbi notes [0] disable [1] enable
[ AK8857VQ] ms1189-e-01 2010/12 -66- luminance bandwidth adjustment luminance bandwidth adjustment c an be performed for mpeg compression etc. the band-limiting filters for pre-compression limiting can be selected by the following register settings. without these filters, the frequency response of the luminance signal is determined by the decimation filter. lumfil[1:0]-bit : settings for luminance bandwidth filter lumfil [1:0]-bit filter characteristic notes [00] no filter. no bandwidth limit. -3db at 6.29mhz [01] narrow -3db at 2.94mhz [10] mid -3db at 3.30mhz [11] wide -3db at 4.00mhz luminance signal decimation filter ???????? luminance bandwidth filter sepia output sepia-colored output of the decoded signal can be obtained by t he following register setting. sepia-bit : settings for sepia output of decoded signal (sub-address 0x14_[6]) sepia ?bit output notes [0] normal [1] sepia output
[ AK8857VQ] ms1189-e-01 2010/12 -67- vbi information decoding the ak8857 decodes closed-captio n, closed-caption-extended, vbid(cgms), and wss signals on the vertical blanking si gnal, and writes the decoded data into a storage register. the ak8857 reads each data bit in request vbi information regist er(r/w)-[3:0] as a decoding request and thereupon enters a data wait state. data detection and decoding to the storage register are then performed which indicates the presence or abs ence of data at status 2 register-[3:0] for host. the host can therefore determine the stored values by reading the respective storage registers. the value in each storage register is retained until a new value is written in by data renewal. for vbid data (cgms-a), the crcc code is decoded and only the arithmetic result is stored in the register. signal type superimposed line notes closed caption line21 525-line closed caption extended data line284 525-line vbid line20 / 283 line20 / 333 525-line 625-line wss line23 625-line the storage registers for each of the signal types are as follows. for stor age bit allocations, please refer to the respective register setting descriptions. closed caption 1 register, closed caption 2 register wss 1 register, wss 2 register extended data 1 register, extended data 2 register vbid 1 register, vbid 2 register 2 request vbi info register 3 xxrq-bit = 1 (decode request start 2 status register 3 read ??? 4??y request t0 ` h??? = 1 no if closed caption : ccrq-bit if closed caption extended : extrq-bit if v bid/ wss : v bw sr q- bit closed caption s?y ccdet- bit closed caption extended s?y ext d et- b it vbid/wss s?y vbwsdet-bit yes ???t0 `h??? ?w??? closed caption s?y2 closed caption 1 ~ 2 register 3 closed caption extended s?y 2 extended data 1 ~ 2 register 3 vbid/wss s?y2 vbid/wss 1 ~ 2 register 3 internal status indicators nosig-bit: indicates pres ence or absence of signal nosig ?bit status of signal input notes [0] signal detected [1] no signal detected
[ AK8857VQ] ms1189-e-01 2010/12 -68- vlock-bit: indicates status of vlock vlock-bit status of synchronization notes [0] synchronized [1] non-synchronized colkilon: indicates status of color killer (on/off) colkilon ?bit status of color killer notes [0] not operation [1] operation sclkmode -bit: indicates status of color killer sclkmode ?bit clock mode notes [00] fixed-clock [01] line-locked [10] frame-locked [11] reserved pkwhite: indicates status of luminance dec ode result after passage through agc block pkwhite ?bit status of luminance decode result notes [0] normal [1] overflow ovcol: indicates status of color decode result after passage through acc block ovcol ?bit status of color decode result notes [0] normal [1] overflow realfld-bit: indicates dec oding signal field status realfld -bit decoding field notes [0] even [1] odd agcsts-bit: indicates status of adaptive agc agcsts -bit status of agc operation notes [0] sync agc operation [1] peak agc operation status 2-ragister: indicates closed caption, extended data, vbid, and wss signal status.
[ AK8857VQ] ms1189-e-01 2010/12 -69- input video status-register: indicates stat us of automatic input signal detection bit register name r/w definition bit 0 ~ bit 1 st_vsf0 ~ st_vsf1 status of video sub-carrier frequency r input signal subca rrier frequency: [ st_vsf1 : st_vsf0 ] ( mhz ) [00] : 3.57954545 (ntsc-m,j) [01] : 3.57561149 (pal-m) [10] : 3.58205625 (pal-nc) [11] : 4.43361875 (pal-b,d,g,h,i,n,60 , ntsc-4.43) bit 2 ~ bit 3 st_vcen0 ~ st_vcen1 status of video color encode r input signal color encode format: [st_vcen1 : st_vcen0] [00] : ntsc [01] : pal [10] : secam [11] : reserved bit 4 st_vlf status of video line frequency r input signal line frequency [0]: 525 line (ntsc-m,j, 4.43, pal-m,60) [1]: 625 line (pal-b,d,g,h,i,n,nc , secam) bit 5 st_bw status of b/w signal r input signal monochrome or non-monochrome : (*1) [0] : non-monochrome detected [1] : monochrome bit 6 undef un_define bit r input signal presenc e or absence (*2) [0] : input signal detected [1] : no input signal detected bit 7 fixed input video standard fixed bit r input signal detection phase (*3) [0] : input signal search in progress [1] : input signal search complete (*1) monochrome auto detection is enabled if the color killer se tting is on(colkill-bit = [1]). st_bw-bit changes to [1] w hen the color killer operates. if the user has deliberately entered the b/w-bit setting sub address 0x01, input signal detection is limited to 525/625 line detection, and onl y the st_vlf information is relevant. (*2) shows results of input signal detection. ? if an input signal is detected, the value is [0]; if no input signal is det ected, the value is [1]. (*3) shows the operating phase of t he automatic input signal detector. the value is [0] while the detection operation is in progress, and [1] when it is completed; thus, when undef-bit = [1], fixed-bit = [0].
[ AK8857VQ] ms1189-e-01 2010/12 -70- the vbi information storage registers are as follows. closed caption 1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 closed caption 2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc15 cc14 cc13 cc12 cc11 cc10 cc9 cc8 wss 1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g2-7 g2-6 g2-5 g2-4 g1-3 g1-2 g1-1 g1-0 wss 2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved g4-13 g4-12 g4-11 g3-10 g3-9 g3-8 extended data 1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext7 ext6 ext5 ext4 ext3 ext2 ext1 ext0 extended data 2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext15 ext14 ext13 ext12 ext11 ext10 ext9 ext8 vbid 1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved vbid1 vbid2 vbid3 vbid4 vbid5 vbid6 vbid 2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbid7 vbid8 vbid9 vbid10 vbid11 vbid12 vbid13 vbid14
[ AK8857VQ] ms1189-e-01 2010/12 -71- 7.device control interface the ak8857 is controlled via i 2 c bus control interface, as described below. [ i2c bus slave address] the i 2 c slave address can be selected by a sela pin setting of either [1000100] or [1000101]. slave address sela pin status msb lsb pulldown [low] 1 0 0 0 1 0 0 r/w pullup [high] 1 0 0 0 1 0 1 r/w [i 2 c control sequence ] (1) write sequence after receiving a write-mode slave address first byte, the ak8857 receives the sub-address in the second byte and data in the subsequent bytes. the write sequence may be single-byte or multi-byte. (a) single-byte write sequence s slave address w a sub address a data a stp 8-bit 1- bit 8-bit 1- bit 8-bit 1- bit (b) multi-byte write sequence (m-bytes, sequential write operation) s slave address w a sub address (n) a data(n) a data (n+1) a data (n+m) a stp 8-bit 1- bit 8-bit 1- bit 8-bit 1- bit 8-bit 1- bit ??????? 8-bit 1- bit (2) read sequence after receiving a read-mode salve address as the first byte, the ak8857 sends data in the second and subsequent bytes. s slave addres s w a sub address (n) a rs slave address ra data1 a data 2 a data3 a ????? 8-bit 1 8-bit 1 8-bit 1 8-bit 1 8-bit 1 8-bit 1 ????????? ??? data n !a stp 8-bit 1 symbols and abbreviations s : start condition rs : repeated start condition a : acknowledge (sda low ) !a : not acknowledge (sda high) stp : stop condition r/w 1 : read 0 : write : received from master device (normally microprocessor) : output by slave device (ak8857)
[ AK8857VQ] ms1189-e-01 2010/12 -72- 8. register definitions sub address register default r/w block function 0x00 input channel select 0x00 r/w common input channel setting 0x01 afe control 0x01 r/w common analog front-end setting 0x02 output control 0x00 r/w common output data setting 0x03 start and delay control 0x00 r/w common output data timing adjustment 0x04 control 1 0x00 r/w common control register type 0x05 control 2 0x00 r/w common control register type 0x06 pedestal level control 0x00 r/w common pedestal level adjustment 0x07 color killer control 0x08 r/w common color killer setting 0x08 image control 0x00 r/w common image control setting 0x09 high slice data set 0xeb r/w co mmon vbi slicer data high setting 0x0a low slice data set 0x10 r/w common vbi slicer data low setting 0x0b pga control 1 0x3e r/w common pga1 gain setting 0x0c pga control 2 0x3e r/w common pga2 gain setting 0x0d output data format a 0x00 r/w a output data format setting 0x0e input video standard a 0x00 r/w a input video signal setting 0x0f ndmode a 0x00 r/w a auto detection limit setting 0x10 output pin control 0 a 0x00 r/w a output pin status setting 0x11 output pin control 1 a 0x00 r/w a output pin status setting 0x12 agc & acc a control 0x00 r/w a agc and acc setting 0x13 control 0 a 0x00 r/w a control register type 0x14 contrast control a 0x80 r/w a contrast adjustment 0x15 brightness control a 0x00 r/w a brightness adjustment 0x16 saturation control a 0x80 r/w a saturation adjustment 0x17 hue control a 0x00 r/w a hue adjustment 0x18 request vbi infomation a 0x00 r/w a vbi interval decode request 0x19 status 1 a r a internal status indicator 0x1a status 2 a r a internal status indicator 0x1b reserved r a reserved 0x1c input video status a r a input signal detection indicator 0x1d closed caption 1 a r a closed caption data indicator 0x1e closed caption 2 a r a closed caption data indicator 0x1f wss 1 a r a wss data indicator 0x20 wss 2 a r a wss data indicator 0x21 extended data 1 a r a cc-extended data indicator 0x22 extended data 2 a r a cc-extended data indicator
[ AK8857VQ] ms1189-e-01 2010/12 -73- sub address register default r/w block function 0x23 vbid 1 a r a vbid data indicator 0x24 vbid 2 a r a vbid data indicator 0x25 output data format a 0x00 r/w b output data format setting 0x26 input video standard b 0x00 r/w b input video signal setting 0x27 ndmode b 0x00 r/w b auto detection limit setting 0x28 output pin control 0 b 0x00 r/w b output pin status setting 0x29 output pin control 1 b 0x00 r/w b output pin status setting 0x2a agc & acc b control 0x00 r/w b agc and acc setting 0x2b control 0 b 0x00 r/w b control register type 0x2c contrast control b 0x80 r/w b contrast adjustment 0x2d brightness control b 0x00 r/w b brightness adjustment 0x2e saturation control b 0x80 r/w b saturation adjustment 0x2f hue control b 0x00 r/w b hue adjustment 0x30 request vbi infomation b 0x00 r/w b vbi interval decode request 0x31 status 1 b r b internal status indicator 0x32 status 2 b r b internal status indicator 0x33 reserved r b reserved 0x34 input video status b r b input signal detection indicator 0x35 closed caption 1 b r b closed caption data indicator 0x36 closed caption 2 b r b closed caption data indicator 0x37 wss 1 b r b wss data indicator 0x38 wss 2 b r b wss data indicator 0x39 extended data 1 b r b cc-extended data indicator 0x3a extended data 2 b r b cc-extended data indicator 0x3b vbid 1 b r b vbid data indicator 0x3c vbid 2 b r b vbid data indicator 0x3d device and revision id r common device id and revision id indicator for all other registers, write-in is prohibited. for all reserved registers, write-in must be limited to the default value. ? common ? is common register to r/w register to a block and b block can be done by regsel bit setting of sub-address?0x00?. for r/w of [input channel select], [pga control 1], [pga control 2], [device and revision id] register, regsel bit setting is not necessary. ?a? is referred to a block register. ?b? is referred to b block register.
[ AK8857VQ] ms1189-e-01 2010/12 -74- 9. register settings overview input channel select register (r/w) [sub address 0x00] input signal channel selection and clock mode selection register. sub address 0x00 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1drv1 p1drv0 regsel ainsel4 ainsel3 ainsel2 ainsel1 ainsel0 default value 0 0 0 0 0 0 0 0 input channel select register definition bit register name r / w definition bit 0 ~ bit 4 ainsel0 ~ ainsel4 analog input select r / w a block and b lock output video signal selection : [ainsel4: ainsel0] [00000]: [a]: ain1(cvbs) , [b]: ain4(cvbs) [00001]: [a]: ain1(cvbs) , [b]: ain3(cvbs) [00010]: [a]: ain1(cvbs) , [b]: ain2(cvbs) [00011]: [a]: ain1(cvbs), [b]: ain1(cvbs) (*2) [00100]: [a]: ain1(cvbs), [b]: non-decode(*1) [00101]: [a]: ain2(cvbs) , [b]: ain4(cvbs) [00110]: [a]: ain2(c vbs), [b]: ain3(cvbs) [00111]: [a]: ain2(cvbs), [b]: ain2(cvbs) (*2) [01000]: [a]: ain2(cvbs) , [b]: ain1(cvbs) [01001]: [a]: ain2(cvbs), [b ]: non-decode (*1) [01010]: [a]: ain3(cvbs) , [b]: ain4(cvbs) [01011]: [a]: ain3(cvbs), [b]: ain3(cvbs) (*2) [01100]: [a]: ain3(c vbs), [b]: ain2(cvbs) [01101]: [a]: ain3(c vbs), [b]: ain1(cvbs) [01110]: [a]: ain3(cvbs), [b]: non-decode (*1) [01111]: [a]: ain4(c vbs), [b]: ain4(cvbs) (*2) [10000]: [a]: ain4(cvbs) , [b]: ain3(cvbs) [10001]: [a]: ain4(cvbs) , [b]: ain2(cvbs) [10010]: [a]: ain4(cvbs) , [b]: ain1(cvbs) [10011]: [a]: ain4(cvbs), [b]: non-decode (*1) [10100]: [a]: non-decode, [b]: ain4(cvbs) (*1) [10101]: [a]: non-decode, [b]: ain3(cvbs) (*1) [10110]: [a]: non-decode, [b]: ain2(cvbs) (*1) [10111]: [a]: non-decode, [b]: ain1(cvbs) (*1) [11000]: [a]: ain1(y) / ain3(c), [b]: non-decode (*1, *2) [11001]: [a]: ain1(y) / ain3(c), [b]: ain1(y) / ain3(c) (*1, *2) [11010]: [a]: ain2(y) / ain4(c), [b]: non-decode (*1, *2) [11011]: [a]: ain2(y) / ain4(c), [b ]: ain2(y) / ain4(c) (*1, *2) [11100]: [a]: non-decode, [b]: ain1(y) / ain3(c) (*1, *2) [11101]: [a]: non-decode, [b]: ain2(y) / ain4(c) (*1, *2)
[ AK8857VQ] ms1189-e-01 2010/12 -75- bit 5 regsel register select r / w common register setting method selection (*2) [0]: a block : write/ read enable [1]: b block : write/ read enable bit 6 ~ bit 7 p1drv0 ~ p1drv1 pvdd1 drive r / w the digital p1 output pin buffer drive setting is set according to pvdd1 input voltage setting.(*3) [p1drv1: p1drv0] [00]: pvdd1 = 3.0 ~ 3.6v [01]: pvdd1 = 2.3 ~ 2.7v [10]: reserved [11]: pvdd1 = 1.7 ~ 2.0v (*1) if [non-decode] is select at the output block, the output pins will be in powersave mode and the internal digital circuit operat ional is stop. this will sa ve the power consumption. (*2) if the output of a block and b block is select ed from the same channel of input video signal, the setting of sub-address0x01 [afe control regi ster] register only enable if regsel=[0] and disable if regsel=[1]. during s-video signal decode, the output block register setting is enable if regsel=[0] and disable if regsel=[1]. (*3) digital p1 pin: data_a[7:0], hd_act_a, vd_act_a, dvalid_a, field_a, data_b[7:0], hd_act_b, vd_act_b, dvalid_b, field_b, dtclk pin.
[ AK8857VQ] ms1189-e-01 2010/12 -76- afe control register (r/w) [sub address 0x01] (common register) analog front end register setting. r/w block is depends on regsel setting of sub-address ?0x00?. sub address 0x01 default value : 0x01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clpwidth1 clpwidth0 clpstat1 clpstat0 udg1 udg0 clpg1 clpg0 default value 0 0 0 0 0 0 0 1 afe control register 1 definition bit register name r / w definition bit 0 ~ bit 1 clpg 0 ~ clpg1 clamp gain r / w set the current value of fine clamp in analog block [00]: min. [01]: middle 1 (default) [10]: middle 2 [11]: max bit 2 ~ bit 3 udg 0 ~ udg 1 up down gain r / w set the current value of rough clamp in analog block. [00]: min. (default) [01]: middle 1 [10]: middle 2 [11]: max bit 4 ~ bit 5 clpstat0 ~ clpstat1 clamp start r / w set the position of clamp pulse [ clpstat1 : clpstat0 ] [00] : center of horizontal sync [01] : (1/128) h delay [10] : (2/128) h advance [11] : (1/128) h advance bit 6 ~ bit 7 clpwidth0 ~ clpwidth1 clamp pulse width r / w set the width of clamp pulse. [ clpwidth1 : clpwidth0 ] [00] : 296nsec [01] : 593nsec [10] : 1.1usec [11] : 2.2usec if the output of a block and b block is selected from the same channel of input video signal, the setting of sub-address0x01 [afe control register] re gister only enable if regsel=[0] and disable if regsel=[1]. during s-video signal decode, the out put block register setting is enabl e if regsel=[0] and disable if regsel=[1].
[ AK8857VQ] ms1189-e-01 2010/12 -77- output control register (r/w) [sub address 0x02] (common register) output data setting register. r/w block is depends on regsel setting of sub-address ?0x00?. sub address 0x02 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbidec1 vbidec0 sllvl trsvsel 601limit vbil2 vbil1 vbil0 default value 0 0 0 0 0 0 0 0 output format register definition bit register name r/w definition bit 0 ~ bit 2 vbil0 ~ vbil2 vertical blanking length r/w vact signal active star ting position adjustment. [ vbil2 : vbil0 ] [000]: default [001]: 1line (2line*) advance [010]: 2line (4line*) advance [011]: 3line (6line*) advance [100]: 4line (8line*) advance [101]: 5line (10line*) advance [110]: 6line (12line*) advance [111]: 7line (14line*) advance bit 3 601limit 601 output limit r/w output data code limit (min-max) setting [0] : 1-254 (y/cb/cr) [1] : 16-235 (y) /16-240 (cb/cr) bit 4 trsvsel time reference signal v select r/w setting of lines for ?time reference signal? v-bit value change in itu-r bt.656 format with 525-line input setting [0]: v=1 (lines 1~9 and 264~272) v=0 (lines 10~263 and 273~525) setting [1]: v=1 (lines 1~19 and 264~282) v=0 (lines 20~263 and 283~525) with 625-line input always (regardless of setting in this register): v=1 (lines 1~22 and 311~335) v=0 (lines 23~310 and 336~623) bit 5 sllvl slice level r/w slice level setting [0] : slice level approx. 25 ire [1] : slice level approx. 50 ire bit 6 ~ bit 7 vbidec0 ~ vbidec1 vbi decode r/w setting for type of data output during interval set in vertical blanking interval register * [ vbidec1 : vbidec0 ] [00] : black level data output [01] : monochrome data output [10] : slice result data output [11] : reserved *only support progressive output size of itu-r bt.601, vga, wvga format.
[ AK8857VQ] ms1189-e-01 2010/12 -78- start and delay control register (r/w) [sub address 0x03] (common register) output data timing adjustment register. r/w block is depends on regsel setting of sub-address ?0x00?. sub address 0x03 default value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vlocksel actsta2 actsta1 actsta0 reserved ycdelay2 ycdelay1 ycdelay0 default value 0 0 0 0 0 0 0 0 start and delay control register definition bit register name r/w definition bit 0 ~ bit 2 ycdelay0 ~ ycdelay2 y/c delay control r/w adjustment of y and c timing. [ ycdelay2 : ycdelay0 ] [001] : y advance 1sample toward c. [010] : y advance 2sample toward c. [011] : y advance 3sample toward c. [000] : no delay and advance. [101] : y delay 3 sample toward c. [110] : y delay 2 sample toward c. [111] : y delay 1 sample toward c. [100] : reserved bit 3 reserved reserved r/w reserved bit 4 ~ bit 6 actsta0 ~ actsta2 active video start control r/w fine-tuning video data dec ode start position by delay or advance in 1-sample units. [actsta2: actsta0] [001]: 1-sample delay [010]: 2-sample delay [011]: 3-sample delay [000]: normal start position [101]: 3-sample advance [110]: 2-sample advance [111]: 1-sample advance [100]: reserved bit 7 vlocksel vlock select r/w select of internal operation with the input signal frame structure [0]: pll sync vlock [1]: direct sync vlock
[ AK8857VQ] ms1189-e-01 2010/12 -79- control 1 register (r/w) [sub address 0x04] (common register) control register setting. r/w block is depends on regsel setting of sub-address ?0x00?. sub address 0x04 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved eavsav clkinv intpoloff reserved uvfilsel ycsep1 ycsep0 default value 0 0 0 0 0 0 0 0 control 1 register definition bit register name r/w definition bit 0 ~ bit 1 ycsep0 ~ ycsep1 yc separation control r/w y/c separation setting [ ycsep1 : ycsep0 ] [00] : adaptive y/c separation [01] : 1-dimensional y/c separation [10] : 2-dimensional y/c separation [11] : reserved bit 2 uvfilsel uv filter select r/w uv filter setting [0]: wide [1]: narrow bit 3 reserved reserved r/w reserved bit 4 intpoloff interpolator mode select r/w pixel interpolator setting [0]: on [1]: off bit 5 clkinv clk invert set r/w dtclk signal output polarity selection [0] : normal output (write in data at rising edge) [1] : data and clock reversed (write in data at falling edge) bit 6 eavsav eav/ sav select r/w eav/sav sync code add setting [0]: sync code is added [1]: not added. bit 7 reserved reserved r/w reserved
[ AK8857VQ] ms1189-e-01 2010/12 -80- control 2 register (r/w) [sub address 0x05] (common register) control register setting. r/w block is depends on regsel setting of sub-address ?0x00?. sub address 0x05 default value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ckilsel stupatoff reserved reserved reserved reserved dpal1 dpal0 default value 0 0 0 0 0 0 0 0 control 2 register definition bit register name r/w definition bit 0 ~ bit 1 dpal0 ~ dpal1 deluxe pal r/w setting for color averaging* (pal phase correction block) [ dpal1 : dpal0 ] [00] : adaptive phase correction on [01] : phase correction on [10] : phase correction off [11] : reserved bit 2 ~ bit 5 reserved reserved r/w reserved bit 6 stupatoff setup auto control off r/w setup auto switching setting (on/off) in auto signal detection mode [0] : auto setup switching on [1] : auto setup switching off bit 7 ckilsel color killer select r/w color killer activation setting [0] : activation when burst color level is below cklvl[3:0]-bits threshold setting [1] : activation when burst color level is below cklvl[3:0]-bits threshold setting or color decode pll lock fails
[ AK8857VQ] ms1189-e-01 2010/12 -81- pedestal level control register (r/w) [sub address 0x06] (common register) pedestal level adjustment setting register. r/w block is depends on regsel setting of sub-address ?0x00?. sub address 0x06 default value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dpcc1 dpcc0 dpct1 dpct0 bklvl3 bklvl2 bklvl1 bklvl0 default value 0 0 0 0 0 0 0 0 pedestal level control register definition bit register name r/w definition bit 0 ~ bit 3 bklvl0 ~ bklvl3 black level r/w setting for change from current pedestal level by adding to or subtracting from black level [ bklvl3 : bklvl0 ] [0001] : add 1 [0010] : add 2 [0011] : add 3 [0100] : add 4 [0101] : add 5 [0110] : add 6 [0111] : add 7 [0000] : default [1000] : subtract 8 [1001] : subtract 7 [1010] : subtract 6 [1011] : subtract 5 [1100] : subtract 4 [1101] : subtract 3 [1110] : subtract 2 [1111] : subtract 1 bit 4 ~ bit 5 dpct0 ~ dpct1 digital pedestal clamp control r/w time-constant setting for digital pedestal clamp [ dpct1 : dpct0 ] [00] : fast [01] : middle [10] : slow [11] : disable bit 6 ~ bit 7 dpcc0 ~ dpcc1 digital pedestal clamp coring control r/w non-sensing bandwidth setting for digital pedestal clamp [ dpcc1 : dpcc0 ] [00] : 1bit [01] : 2bit [10] : 3bit [11] : no non-sensing band
[ AK8857VQ] ms1189-e-01 2010/12 -82- color killer control register (r/w) [sub address 0x07] (common register) color killer setting register r/w block is depends on regsel setting of sub-address ?0x00?. sub address 0x07 default value : 0x08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 colkill contsel ckscm1 ckscm0 cklvl3 cklvl2 cklvl1 cklvl0 default value 0 0 0 0 1 0 0 0 color killer control register definition bit register name r/w definition bit 0 ~ bit 3 cklvl0 ~ cklvl3 color killer level control r/w burst level setting for co lor killer activation default value, approx. ? 23 db bit 4 ~ bit 5 ckscm0 ~ ckscm1 color killer level for secam r/w burst level setting for color killer activation in secam mode adds 2 bits to cklvl[3:0] bit 6 contsel contrast select r/w contrast selector [0] : toward luminance of 128 [1] : toward luminance of 0 bit 7 colkill color killer set r/w color killer on/off setting [0] : enable [1] : disable
[ AK8857VQ] ms1189-e-01 2010/12 -83- image control register (r/w) [sub address 0x08] (common register) sharpness control, luminance bandwidth filter control, sepia color output setting and vbi interval setting register. r/w block is depends on regsel setting of sub-address ?0x00?. sub address 0x08 default value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbiimgctl sepia lumfil1 lumfil0 shcore1 shcore0 sharp1 sharp0 default value 0 0 0 0 0 0 0 0 image control register definition bit register name r/w definition bit 0 ~ bit 1 sharp0 ~ sharp1 sharpness control r/w sharpness control (filter effect) setting [ sharp1 : sharp0 ] [00] : no filtering [01] : min effect [10] : middle effect [11] : max effect bit 2 ~ bit 3 shcore0 ~ shcore1 sharpness coring r/w setting for level of coring after passage through sharpness filter enabled except with [sharp1:sharp0] register setting of [00] [ shcore1 : shcore0 ] [00] : no coring [01] : 1lsb [10] : 2lsb [11] : 3lsb bit 4 ~ bit 5 lumfil0 ~ lumfil1 luminance filter r/w setting for luminance band limit filter [ lumfil1 : lumfil0 ] [00] : no filtering [01] : narrow [10] : mid [11] : wide bit 6 sepia sepia output r/w setting (on/off) for sepia coloring of decode results * [0]: normal output [1]: sepia output bit 7 vbiimgctl vbi image control r/w setting (on/off) for image adjustment during brightness and contrast adjustment vbi* [0]: image adjustment inactive during vbi [1]: image adjustment active during vbi * doa register of sub-address ?0x10? and dob register of sub-address ?0x28? setting takes priority regardless to above sepia register setting.
[ AK8857VQ] ms1189-e-01 2010/12 -84- high slice data set register (r/w) [sub address 0x09] (common register) register for setting sliced data from vbi s licer to high value (default code is 235). r/w block is depends on regsel setting of sub-address ?0x00?. sub address 0x09 default value : 0xeb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h7 h6 h5 h4 h3 h2 h1 h0 default value 1 1 1 0 1 0 1 1 high slice data set register definition bit register name r/w definition bit 0 ~ bit 7 h0 ~ h7 high data 0~7 set r/w register for setting sliced data from vbi slicer to high value (default code is 235) important: corresponds to 601 special code if set to 0x00 or 0xff low slice data set register (r/w) [sub address 0x0a] (common register) register for setting sliced data from vbi s licer to low value (default code is 16) r/w block is depends on regsel setting of sub-address ?0x00?. sub address 0x0a default value : 0x10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l7 l 6 l 5 l 4 l 3 l 2 l 1 l 0 default value 0 0 0 1 0 0 0 0 low slice data set register definition bit register name r/w definition bit 0 ~ bit 7 l0 ~ l7 low data 0~7 set r/w register for setting sliced data from vbi slicer to low value (default code is 16) important: corresponds to 601 special code if set to 0x00 or 0xff
[ AK8857VQ] ms1189-e-01 2010/12 -85- pga control 1 register (r/w) [sub address 0x0b] pga1 control register in case of cvbs signal decode, its cont rol the gain setting for a block output. in case of s-videosignal decode, its c ontrol the gain setting for y signal output. sub address 0x0b default value : 0x1f bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pga1_7 pga1_6 pga1_5 pga1_4 pga1_3 pga1_2 pga1_1 pga1_0 default value 0 0 1 1 1 1 1 0 pga control 1 register definition bit register name r/w definition bit 0 ~ bit 7 pga1_0 ~ pga1_7 pga1 gain set r/w pga gain setting, in steps of approx. 0.1 db *1 when cvbs signal decode, if t he output of a block and b block is the same video signal, only pga1 control register is enable and pga2 control register is disable. *2 when cvbs signal decode, if the output block is selected to [non-decode], the gain setting is set to ?0x00? value. pga control 2 register (r/w) [sub address 0x0c] pga2 control register in case of cvbs signal decode, its cont rol the gain setting for b block output. in case of s-videosignal decode, its c ontrol the gain setting for c signal output. sub address 0x0c default value : 0x1f bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pga2_7 pga2_6 pga2_5 pga2_4 pga2_3 pga2_2 pga2_1 pga2_0 default value 0 0 1 1 1 1 1 0 pga control 2 register definition bit register name r/w definition bit 0 ~ bit 7 pga2_0 ~ pga2_7 pga2 gain set r/w pga gain setting, in steps of approx. 0.1 db *1 when cvbs signal decode, if the ou tput of a block and b block is the same vi deo signal, only pga1 control register is enable and pga2 control register is disable. *2 when cvbs signal decode, if the ou tput block is selected to [non- decode], the gain se tting is set to ?0x00? value.
[ AK8857VQ] ms1189-e-01 2010/12 -86- output data format a register (r/w) [sub address 0x0d] (a block register) output data format a register (r/w) [sub address 0x25] (b block register) output data format setting register. this register is applied to set the a block output data. sub address 0x0d, 0x25 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved odeva odevb odforma3 odformb3 odforma2 odformb2 odforma1 odformb1 odforma0 odformb0 default value 0 0 0 0 0 0 0 0 output data format a register definition bit register name r / w definition bit 0 ~ bit 3 odforma/b0 ~ odforma/b3 output data format_a/b r / w output data format selection : [odforma/b3: odforma/b0] [0000] : 601 (interlace) (525 line : 720x487) (625 line : 720x576) [0001] : 601 (progressive, 60frm/s) (525 line : 720x487) (625 line : 720x576) [0010] : 601 (progressive, 30frm/s) (525 line : 720x487) (625 line : 720x576) [0011]: wvga (interlace) (800x480) [0100]: wvga (progressive, 60frm/s) (800x480) [0101]: wvga (progressive, 30frm/s) (800x480) [0110]: vga (interlace) (640x480) [0111]: vga (progressive, 60frm/s) (640x480) [1000]: vga (progressive, 30frm/s) (640x480) [1001]: wqvga (progressive, 30frm/s) (400x240) [1010]: qvga (progressive, 30frm/s) (320x240) [1011]: ega (progressive, 30frm/s) (400x234) [1100]: wega1 (progressive, 30frm/s) (480x240) [1101]: wega2 (progressive, 30frm/s) (480x234) bit 4 odeva/b odd even select_a/b r / w decode field selection during (progressive, 30frm/s) output. [0]: odd field [1]: even field bit 5 ~ bit 7 reserved reserved r / w reserved
[ AK8857VQ] ms1189-e-01 2010/12 -87- input video standard a register (r/w) [sub address 0x0e] (a block register) input video standard a register (r/w) [sub address 0x26] (b block register) this register is applied to set the analog input signal. sub address 0x0e, 0x26 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 autodeta autodetb setupa setupb bwa bwb vlfa vlfb vcena1 vcenb1 vcena0 vcenb0 vscfa1 vscfb1 vscfa0 vscfb0 default value 0 0 0 0 0 0 0 0 input video standard a/b register definition bit register name r/w definition bit 0 ~ bit 1 vscfa/b 0 ~ vscfa/b 1 video sub-carrier frequency_a/b r/w input video signal subcarrier frequency setting [vscfa/b 1 : vscfa/b 0 ] ( mhz ) [00] : 3.57954545 (ntsc-m,j) [01] : 3.57561149 (pal-m) [10] : 3.58205625 (pal-nc) [11] : 4.43361875 (pal-b,d,g,h,i,n,60,ntsc-4.43, secam)* 1 bit 2 ~ bit 3 vcena/b 0 ~ vcena/b 1 video color encode_a/b r/w input signal color encode format setting [vcena/b 1 : vcena/b 0] [00] : ntsc [01] : pal [10] : secam [11] : reserved bit 4 vlfa/b video line frequency_a/b r/w input signal line frequency setting [0] : 525 line (ntsc-m,j , ntsc-4.43 , pal-m,60) [1] : 625 line (pal-b,d,g,h,i,n , pal-nc , secam) bit 5 bwa/b black & white_a/b r/w monochrome mode (on/off) setting * 2 [0] : monochrome mode off [1] : monochrome mode on bit 6 setupa/b setup_a/b r/w setup process setting [0] : process as input signal with no setup [1] : process as input signal with setup bit 7 autodeta/b video standard auto detect_a/b r/w input signal auto detection setting * 3 [0]: off (auto detection disabled; set manually) [1]: on (auto detection enabled) * 1 for secam input signal, change vscf[1:0] setting to [11]. * 2 doa register of sub-address ?0x10? and dob register of sub-address ?0x28? setting takes priority regardless to above bw register setting. * 3 ?auto detection function? must not use when it is being operated on direct sync vlock (sub-address0x03[7]=1).
[ AK8857VQ] ms1189-e-01 2010/12 -88- ndmode a register (r/w) [sub address 0x0f] (a block register) ndmode b register (r/w) [sub address 0x27] (b block register) for limiting auto input video signal detec tion candidates of a block output data. sub address 0x0f, 0x27 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nd625la nd625lb nd525la nd525lb ndpal60a ndpal60b ndnt443a ndnt443b reserved reserved ndsecama ndsecamb ndpalnca ndpalncb ndpalma ndpalmb default value 0 0 0 0 0 0 0 0 ndmode a/b register definition bit register name r/w definition bit 0 ndpalma/b no detect pal-m_a /b r/w [0] : pal-m candidate [1] : pal-m non-candidate bit 1 ndpalnca/b no detect pal-nc_a/b r/w [0] : pal-nc candidate [1] : pal-nc non-candidate bit 2 ndsecama/b no detect secam_a/b r/w [0] : secam candidate [1] : secam non-candidate bit 3 reserved reserved r/w reserved bit 4 ndnt443a/b no detect ntsc-4.43_a/b r/w [0] : ntsc-4.43 candidate [1] : ntsc-4.43 non-candidate bit 5 ndpal60a/b no detect pal-60_a/b r/w [0] : pal-60 candidate [1] : pal-60 non-candidate bit 6 nd525la/b no detect 525line_a/b r/w [0] : 525 line candidate [1] : 525 line non-candidate bit 7 nd625la/b no detect 625line_a/b r/w [0] : 625 line candidate [1] : 625 line non-candidate in making the above register settings, the following restrictions are apply, [1] setting both ndnt443a/b (bit 4) and ndpal60a/b (bit 5) to [1] (high) is prohibited. [2] setting both nd525la/b (bit 6) and nd625la/b (bit 7) to [1] (high) is prohibited. [3] to limit candidate formats, it is necessary to have the auto detection mode off while first setting the register to non-limited signal status and next the ndmode settings, and then setting the auto detection mode to on.
[ AK8857VQ] ms1189-e-01 2010/12 -89- output pin control 0 a register (r/w) [sub address 0x10] (a block register) output pin control 0 b register (r/w) [sub address 0x28] (b block register) a block output pin output status setting sub address 0x10, 0x28 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved fla flb hdactla hdactlb nla nlb dvalidla dvalidlb vdactla vdactlb doa1 dob1 doa0 dob0 default value 0 0 0 0 0 0 0 0 output control 0 a/b register definition bit register name r/w definition bit 0 ~ bit 1 doa/b 0 ~ doa/b 1 data output _a/b r/w [00]: normal output [01]: data_a/b [7: 0] pin output fixed at low [10]: black level output [11]: blue level output bit 2 vdactla/b vd/ vact low_a/b r/w [0] : normal output [1]: vd_act_a/b pin output fixed at low. bit 3 dvalidla/b dvalid low_a/b r/w [0] : normal output [1]: dvalid_a/b pin output fixed at low. bit 4 nla/b nsig low_a/b r/w [0] : normal output [1] : nsig_a/b pin output fixed at low bit 5 hdactla/b hd/hact low_a/b r/w [0] : normal output [1]: hd_act_a/b pin output fixed at low. bit 6 fla/b field_a/b r/w [0] : normal output [1] : field_a/b pin output fixed at low bit 7 reserved reserved r/w reserved note: output control via pins oe_a , oe_b, pdn, rstn and ainsel[4:0] (non-decode) takes priority, regardless of the above settings.
[ AK8857VQ] ms1189-e-01 2010/12 -90- output pin control 1 a register (r/w) [sub address 0x11] (a block register) output pin control 1 b register (r/w) [sub address 0x29] (b block register) a block output pin status setting register. sub address 0x11, 0x29 default value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved hdactsela hdactselb vdactsela vdactselb fielda fieldb dvalida dvalidb vdacta vdactb hdacta hdactb default value 0 0 0 0 0 0 0 0 output control 1 a/b register definition bit register name r/w definition bit 0 hdacta/b hd_act_a/b pin polarity r/w hd_act_a/b pin output polarity setting. [0] : active low [1] : active high bit 1 vdacta/b vd_act_a/b pin polarity r/w vd_act_a/b pin output polarity setting. [0]: active low [1]: active high bit 2 dvalida/b dvalid_a/b pin polarity r/w dvalid_a/b pin output polarity setting. [0]: active low [1]: active high bit 3 fielda/b field_a/b pin polarity r/w field_a/b pin output polarity setting. [0]: active low [1]: active high bit 4 vdactsela/b vd/ vact select_a/b r/w vd_act_a/b pin output signal selection : [0] : vd signal is output. [1] : vact signal is output. bit 5 hdactsela/b hd/ hact select_a/b r/w hd_act_a/b pin output signal selection : [0] : hd signal is output. [1] : hact signal is output. bit 6 ~ bit 7 reserved reserved r/w reserved note: output control via pins oe _a, oe_b, pdn and rstn takes priority, regardless of the above settings.
[ AK8857VQ] ms1189-e-01 2010/12 -91- agc & acc a control register (r/w) [sub address 0x12] (a block register) agc & acc b control register (r/w) [sub address 0x2a] (b block register) agc and acc setting register. sub address 0x12, 0x2a default value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 accfrza accfrzb acca1 accb1 acca0 accb0 agcfrza agcfrzb agcca1 agccb1 agcca0 agccb0 agcta1 agctb1 agcta0 agctb0 default value 0 0 0 0 0 0 0 0 agc & acc a/b control register definition bit register name r/w definition bit 0 ~ bit 1 agcta/b 0 ~ agcta/b 1 agc time constant_a/b r/w agc time constant (t) setting* (if disabled, pga can be set manually) [ agct1 : agct0 ] [00] : disable [01] : fast [ t = 1field ] [10] : middle [ t =7fields ] [11] : slow [ t = 29fields ] bit 2 ~ bit 3 agcca/b 0 ~ agcca/b 1 agc coring control_a/b r/w agc non-sensing bandwidth (lsb) setting [ agcc1 : agcc0 ] [00] : 2lsb [01] : 3lsb [10] : 4lsb [11] : no non-sensing band bit 4 agcfrza/b agc freeze_a/b r/w agc freeze function (on/off) setting (agc set values are saved during freeze) [0] : non-frozen [1] : frozen bit 5 ~ bit 6 accta/b 0 ~ accta /b 1 acc time constant_a/b r/w acc time constant (t) setting [ acct1 : acct0 ] [00] : disable [01] : fast [ t = 2fields ] [10] : middle [ t =8fields ] [11] : slow [ t = 30fields ] bit 7 accfrza/b acc freeze_a/b r/w acc freeze function (on/off) setting (acc set values are saved during freeze) [0] : non-frozen [1] : frozen
[ AK8857VQ] ms1189-e-01 2010/12 -92- control 0 a register (r/w) [sub address 0x13] (a block register) control 0 b register (r/w) [sub a ddress 0x2b] (b block register) sub address 0x13, 0x2b default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved nsigmda1 nsigmdb1 nsigmda0 nsigmdb0 c443fila1 c443filb1 c443fila0 c443filb0 c358fila1 c358filb1 c358fila0 c358filb0 agctla agctlb default value 0 0 0 0 0 0 0 0 control 0 a/b register definition bit register name r/w definition bit 0 agctla/b agc transition level_a/b r/w transition speed setting, between peak agc and sync agc [0] : quick [1] : slow bit 1 ~ bit 2 c358fila /b 0 ~ c358fila /b 1 c filter_358 select_a/b r/w c-filter bandwidth setting, for 3.58 mhz subcarrier system signal [c358fila/b 1 : c358fila/b 0 ] [00] : 3.58 narrow [01] : 3.58 medium [10] : 3.58 wide [11] : reserved bit 3 ~ bit 4 c443fila /b 0 ~ c443fila/b 1 c filter_443 select_a/b r/w c-filter bandwidth setting, for 4.43 mhz subcarrier system signal [c443fila/b 1 : c443fila/b 0 ] [00] : 4.43 narrow [01] : 4.43 medium [10] : 4.43 wide [11] : reserved bit 5 ~ bit 6 nsigmda/b 0 ~ nsigmda/b 1 no signal output mode_a/b r/w setting for output on no-signal detection * [nsigmda/b 1 : nsigmda/b 0] [00] : black-level output [01] : blue-level (blueback) output [10] : input status (sandstorm) output [11] : reserved bit 7 reserved reserved r/w reserved * doa/b[1:0] register of sub-address?0x01/0x28? takes priority regardless to no-signal detection setting adjustment above when the doa/b[1:0] register value is set other than [00].
[ AK8857VQ] ms1189-e-01 2010/12 -93- contrast control a register (r/w) [s ub address 0x14] (a block register) contrast control b register (r/w) [s ub address 0x2c] (b block register) contrast adjustment setting register. sub address 0x14, 0x2c default value: 0x80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 conta7 contb7 conta6 contb6 conta5 contb5 conta4 contb4 conta3 contb3 conta2 contb2 conta1 contb1 conta0 contb0 default value 1 0 0 0 0 0 0 0 contrast control a/b register definition bit register name r/w definition bit 0 ~ bit 7 conta/b 0 ~ conta/b 7 contrast control_a/b r/w register for contrast adjustment in steps of 1/128 in range 1~255/128 from default value of 0x80 brightness control a register (r/w) [sub address 0x15] (a block register) brightness control b register (r/w) [s ub address 0x2d] (b block register) brightness adjustment setting register sub address 0x15, 0x2d default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bra7 brb7 bra6 brb6 bra5 brb5 bra4 brb4 bra3 brb3 bra2 brb2 bra1 brb1 bra0 brb0 default value 0 0 0 0 0 0 0 0 brightness control a/b register definition bit register name r/w definition bit 0 ~ bit 7 bra/b0 ~ bra/b7 brightness control_a/b r/w register for brightness adjustment in steps of 1 by 8-bit code setting in 2?s complement
[ AK8857VQ] ms1189-e-01 2010/12 -94- saturation control a register (r/w) [sub address 0x16] (a block register) saturation control b register (r/w) [sub address 0x2e] (b block register) saturation adjustment setting register sub address 0x16, 0x2e default value: 0x80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sata7 satb7 sata6 satb6 sata5 satb5 sata4 satb4 sata3 satb3 sata2 satb2 sata1 satb1 sata0 satb0 default value 1 0 0 0 0 0 0 0 saturation control a/b register definition bit register name r/w definition bit 0 ~ bit 7 sata/b0 ~ sata/b7 saturation control_a/b r/w register for saturation level adjustment in steps of 1/128 in range 1~255/128 from default value of 0x80 (cvbs or s-video input) hue control a register (r/w) [sub address 0x17] (a block register) hue control b register (r/w) [sub address 0x2f] (b block register) hue adjustment setting register. sub address 0x17, 0x2f default value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 huea7 hueb7 huea6 hueb6 huea5 hueb5 huea4 hueb4 huea3 hueb3 huea2 hueb2 huea1 hueb1 huea0 hueb0 default value 0 0 0 0 0 0 0 0 hue control a/b register definition bit register name r/w definition bit 0 ~ bit 7 huea/b0 ~ huea/b7 hue control_a/b r/w register for hue adjustment in steps of 1/256 in range 45 in 2?s complement
[ AK8857VQ] ms1189-e-01 2010/12 -95- request vbi infomation a register (r/w) [sub address 0x18] (a block register) request vbi infomation b register (r/w) [sub address 0x30] (b block register) data decode request during vbi interval setting register. sub address 0x18, 0x30 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved wssrqa wssrqb vbidrqa vbidrqb extrqa extrqb ccrqa ccrqb default value 0 0 0 0 0 0 0 0 request vbi infomation a/b register definition bit register name r/w definition bit 0 ccrqa/b closed caption decode request_a/b r/w setting (on/off) for closed caption decode request [0] : no request (off) [1] : request (on) bit 1 extrqa/b extended data decode request_a/b r/w setting (on/off) for extended data decode request [0] : no request (off) [1] : request (on) bit 2 vbidrqa/b vbid decode request_a/b r/w setting (on/off) for vbid decode request [0] : no request (off) [1] : request (on) bit 3 wssrqa/b wss decode request_a /b r/w setting (on/off) for wss decode request [0] : no request (off) [1] : request (on) bit 4 ~ bit 7 reserved reserved r/w reserved
[ AK8857VQ] ms1189-e-01 2010/12 -96- status 1 a register (r) [sub address 0x19] (a block register) status 1 b register (r) [sub address 0x31] (b block register) sub address 0x19, 0x31 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ovcola ovcolb pkwhitea pkwhiteb reserved reserved cplla cpllb colkilona colkilonb frmstda frmstdb vlocka vlockb nosiga nosigb status 1 a/b register definition bit register name r/w definition bit 0 nosiga/b no signal_a/b r input signal indicator [0] : input signal present [1] : input signal absent bit 1 vlocka/b video locked_a/b r input signal vlock synchronization status indicator [0]: input signal synchronized [1]: input signal non-synchronized bit 2 frmstda/b frame standard_a/b r input signal interlace status indicator [0]: input signal 525/625 interlaced [1]: input signal not 525/625 interlaced bit 3 colkilona/b color killer_a/b r color killer status indicator * 1 [0]: color killer not operation [1]: color killer operation bit 4 cplla/b color pll lock_a/b pll clock locked status indicator [0]: no locked [1]: locked bit 5 reserved reserved r reserved bit 6 pkwhitea/b peak white detection_a/b r luminance decode result flow status indicator,after passage through agc block [0]: normal [1]: overflow bit 7 ovcola/b over color level_a/b r color decode result flow status indicator, after passage through acc block* 2 [0]: normal [1]: overflow (excessive color signal input)
[ AK8857VQ] ms1189-e-01 2010/12 -97- status 2 a register (r) [sub address 0x1a] (a block register) status 2 b register (r) [sub address 0x32] (b block register) sub address 0x1a, 0x32 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved agcstsa agcstsb realflda realfldb wssdeta wssdetb vbiddeta vbiddetb extdeta extdetb ccdeta ccdetb status 2 a/b register definition bit register name r/w definition bit 0 ccdeta/b closed caption detect_a/b r indicator for presence of decoded data in closed caption 1 2 register [0]: no closed capt ion data present [1]: closed caption data present bit 1 extdeta/b extended data detect_a/b r indicator for presence of decoded data in extended data 1,2 register 0]: no extended data present [1]: extended data present bit 2 vbiddeta/b vbid data detect_a/b r indicator for presence of decoded data in vbid 1,2 register [0]: no vbid data present [1]: vbid data present bit 3 wssdeta/b wss data detect_a/b r indicator for presence of decoded data in wss 1,2 register [0]: no wss data present [1]: wss data present bit 4 realflda/b real field_a/b r input signal field status (even/odd) indicator [0] : even field [1] : odd field bit 5 agcstsa/b agc status_a/b r [0] : sync agc active [1] : peak agc active * bit 6 ~ bit 7 reserved reserved r reserved
[ AK8857VQ] ms1189-e-01 2010/12 -98- input video status a register (r) [sub address 0x1c] (a block register) input video status b register (r) [sub address 0x34] (b block register) sub address 0x1c, 0x34 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fixeda undefa st_b/wa st_vlfa st_vcena1 st_vcena0 st_vsfa1 st_vsfa0 fixedb undefb st_b/wb st_vlfb st_vcenb1 st_vcenb0 st_vsfb1 st_vsfb0 input video status a/b register definition bit register name r/w definition bit 0 ~ bit 1 st_vsfa/b 0 ~ st_vsfa/b 1 status of video sub-carrier frequency_a/b r input video signal subcarrier frequency indicator [ st_vsfa/b 1 : st_vsfa/b 0 ] ( mhz ) [00] : 3.57954545 (ntsc-m,j) [01] : 3.57561149 (pal-m) [10] : 3.58205625 (pal-nc) [11] : 4.43361875 (pal-b,d,g,h,i,n,60, ntsc-4.43, secam*) bit 2 ~ bit 3 st_vcena/b 0 ~ st_vcena/b 1 status of video color encode_a/b r input signal color encode format indicator [st_vcen1 : st_vcen0] [00] : ntsc [01] : pal [10] : secam [11] : reserved bit 4 st_vlfa/b status of video line frequency_a/b r input signal line number indicator [0] : 525 line (ntsc-m,j , ntsc-4.43 , pal-m,60) [1] : 625 line (pal-b,d,g,h,i,n,nc, secam) bit 5 st_bwa/b status of b/w signal_a/b r input signal monochrome indicator [0]: not monochrome [1]: monochrome bit 6 undefa/b un_define_a/b r input signal detection indicator [0]: input signal detected [1]: input signal not detected bit 7 fixeda/b input video standard fixed_a/b r input signal detection process status [0]: detection process in progress [1]: detection process completed *if secam input signal is detect ed, st_vscf[1:0] goes to [11].
[ AK8857VQ] ms1189-e-01 2010/12 -99- closed caption 1 a register (r) [sub address 0x1d] (a block register) closed caption 1 b register (r) [sub address 0x35] (b block register) closed caption data storage register sub address 0x1d, 0x35 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cca7 ccb7 cca6 ccb6 cca5 ccb5 cca4 ccb4 cca3 ccb3 cca2 ccb2 cca1 ccb1 cca0 ccb0 closed caption 2 a register (r) [sub address 0x1e] (a block register) closed caption 2 b register (r) [sub address 0x36] (b block register) closed caption data storage register sub address 0x1e, 0x36 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cca15 ccb15 cca14 ccb14 cca13 ccb13 cca12 ccb12 cca11 ccb11 cca10 ccb10 cca ccb cca8 ccb8 wss 1 a register (r) [sub address 0x1f] (a block register) wss 1 b register (r) [sub address 0x37] (b block register) wss data storage register sub address 0x1f, 0x37 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ga2-7 ga2-6 ga2-5 ga2-4 ga1-3 ga1-2 ga1-1 ga1-0 gb2-7 gb2-6 gb2-5 gb2-4 gb1-3 gb1-2 gb1-1 gb1-0 wss 2 a register (r) [sub address 0x20] (a block register) wss 2 b register (r) [sub address 0x38] (b block register) wss data storage register sub address 0x20, 0x38 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved ga4-13 gb4-13 ga4-12 gb4-12 ga4-11 gb4-11 ga3-10 gb3-10 ga3-9 gb3-9 ga3-8 gb3-8
[ AK8857VQ] ms1189-e-01 2010/12 -100- extended data 1 a register (r) [sub address 0x21] (a block register) extended data 1 b register (r) [sub address 0x39] (b block register) closed caption extended data storage register sub address 0x21, 0x39 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 exta7 extb7 exta6 extb6 exta5 extb5 exta4 extb4 exta3 extb3 exta2 extb2 exta1 extb1 exta0 extb0 extended data 2 a register (r) [sub address 0x22] (a block register) extended data 2 b register (r) [sub address 0x3a] (b block register) closed caption extended data storage register sub address 0x22, 0x3a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 exta15 extb15 exta14 extb14 exta13 extb13 exta12 extb12 exta11 extb11 exta10 extb10 exta9 extb9 exta8 extb8 vbid 1 a register (r) [sub address 0x23] (a block register) vbid 1 b register (r) [sub address 0x3b] (b block register) vbid data storage register sub address 0x23, 0x3b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved vbida1 vbidb1 vbida2 vbidb2 vbida3 vbidb3 vbida4 vbidb4 vbida5 vbidb5 vbida6 vbidb6 vbid 2 a register (r) [sub address 0x24] (a block register) vbid 2 b register (r) [sub address 0x3c] (b block register) vbid data storage register sub address 0x24, 0x3c bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbida7 vbidb7 vbida8 vbidb8 vbida9 vbidb9 vbida10 vbidb10 vbida11 vbidb11 vbida12 vbidb12 vbida13 vbidb13 vbida14 vbidb14
[ AK8857VQ] ms1189-e-01 2010/12 -101- device and revision id register (r) [sub address 0x3d] device id and revision indicator device id: [0x39] revision id: initially 0x00; revision number change s only when control software should be modified. sub address 0x3d bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev1 rev0 did5 did4 did3 did2 did1 did0 default value 0 0 1 1 1 0 0 1 device and revision id register definition bit register name r/w definition bit 0 ~ bit 5 did0 ~ did5 device id r device id indicator (0x39) bit 6 ~ bit 7 rev0 ~ rev1 revision id r revision id i ndicator (initially 0x00)
[ AK8857VQ] ms1189-e-01 2010/12 -102- 10. system connection example 47 30 ain1~4 0.033uf 0.1uf 0.1uf vrp vcom vrn sd a scl rstn pdn micro processor (i 2 c controller) oe_a data_a[7..0] dtclk dvalid_a vd_act_a hd_act_a analog gnd digital gnd test0 AK8857VQ iref video in pvdd1 pvdd1 test1 y??2
? 0.1uf 10uf pvdd2 pull ? up 0.1uf xti 27mhz xto 22pf 22pf sela pvdd2 pvdd2 0.1uf 10uf dvdd dvdd 0.1uf 10uf dvss dvss dvss avdd avdd 0.1uf 10uf avss nsig_ a oe_b nsig_b field_a data_b[7..0] dvalid_b vd_act_b hd_act_b field_b
[ AK8857VQ] ms1189-e-01 2010/12 -103- 11. package 116 17 32 33 48 49 64 0.20.1 10.00.2 12.00.2 12.00.2 10.00.2 0.5 m 0.08 1.25typ 0.10 0.50.2 1.40.2 1.85max 0.1 0.15 0.1 0 b 10b 0.15 0.1 0.05 s s
[ AK8857VQ] ms1189-e-01 2010/12 -104- 12. marking 1 a km AK8857VQ xxxxxxx akm: akm logo AK8857VQ: marketing code xxxxxxx (7 digits): date code
[ AK8857VQ] ms1189-e-01 2010/12 -105- these products and their specifications are subject to c hange without notice. before considering any use or applicati on, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any informat ion contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariff s, currency exchange, or strategic materials. akm products are neither intended nor authoriz ed for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written cons ent of the representative director of akm. as used here: (a) a hazard related device or syst em is one designed or intended for life support or maintenance of safety or for app lications in medicine, aer ospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of t he buyer or distributor of an akm product who distributes, disposes of, or otherwise places the produc t with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hol d akm harmless from any and all claims arising from the use of said produc t in the absence of such notification. important notice

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